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Dynamically Spawning Speculative Threads to Improve Speculative Path Execution

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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 8631))

Abstract

Branch misprediction, as one of scaling bottlenecks, has a significant effect on the performance of thread-level speculation. Due to ambiguous control and data dependences, it is still hard for the compiler to extract more efficient threads from the hard-to-predict branches by means of either conservative single path-based thread selection or aggressive thread optimization. Thus, this paper proposes a novel dynamic speculative path scheme to dynamically determine the right speculative path at runtime. It relies on compiler to select and optimize all frequent subpaths greedily, and attempts to generate speculative threads on them using the modified FP-growth algorithm. Based on the path-based performance prediction, the best speculative path is always dynamically chosen to parallelize. We have examined our approach using ODLEN benchmarks. Compared to the single speculative path scheme, it can achieve comparable or better performance.

This work is supported by National Nature Science Foundation of China(NSFC) under Grant No.61173040 and Doctoral Fund of Ministry of Education of China under Grant No.20130201110012.

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References

  1. Fp-growth algorithm, http://en.wikipedia.org/wiki/Association_rule_learning

  2. Olden benchmark suite, http://www.cs.preceton.edu/mcc/odlen.html

  3. The suif compiler system. suif group, stanford, http://suif.stanford.edu

  4. The suif control flow graph library, http://www.eecs.harvard.edu/hube/softwa-re/v130/cfg.html

  5. Bhowmik, A., Franklin, M.: A general compiler framework for speculative multithreaded processors. IEEE Transactions on Parallel and Distributed Systems 15(8), 713–724 (2004)

    Article  Google Scholar 

  6. Chen, Z., Zhao, Y.-L., Pan, X.-Y., Dong, Z.-Y., Gao, B., Zhong, Z.-W.: An overview of prophet. In: Hua, A., Chang, S.-L. (eds.) ICA3PP 2009. LNCS, vol. 5574, pp. 396–407. Springer, Heidelberg (2009)

    Chapter  Google Scholar 

  7. Gandhi, A., Akkary, H., Srinivasan, S.: Reducing branch misprediction penalty via selective branch recovery. In: Proceedings of the 10th International Symposium on High Performance Computer Architecture, pp. 254–264. IEEE (2004)

    Google Scholar 

  8. Gao, L., Li, L., Xue, J., Yew, P.C.: Seed: A statically greedy and dynamically adaptive approach for speculative loop execution. IEEE Transactions on Computers 62(5), 1004–1016 (2013)

    Article  MathSciNet  Google Scholar 

  9. Iwama, C., Barli, N.D., Sakai, S., Tanaka, H.: Improving conditional branch prediction on speculative multithreading architectures. In: Sakellariou, R., Keane, J.A., Gurd, J.R., Freeman, L. (eds.) Euro-Par 2001. LNCS, vol. 2150, pp. 413–417. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  10. Jacobson, Q., Bennett, S., Sharma, N., Smith, J.: Control flow speculation in multiscalar processors. In: Proceedings of the IEEE Symposium on High-Performance Computer Architecture, pp. 218–229. IEEE, San Antonio (1997)

    Google Scholar 

  11. Luo, Y., Packirisamy, V., Hsu, W.C., Zhai, A., Mungre, N., Tarkas, A.: Dynamic performance tuning for speculative threads. In: Proceedings of the 36th Annual International Symposium on Computer Architecture, pp. 462–473. ACM, New York (2009)

    Google Scholar 

  12. Malik, K., Agarwal, M., Stone, S., Woley, K., Frank, M.: Branch-mispredict level parallelism (blp) for control independence. In: IEEE 14th International Symposium on High Performance Computer Architecture, Lake City, UT, pp. 62–73 (2008)

    Google Scholar 

  13. Pan, X., Zhao, Y., Chen, Z., Wang, X., Wei, Y., Du, Y.: A thread partitioning method for speculative multithreading. In: Proceedings of the International Conference on Scalable Computing and Communications, pp. 285–290. IEEE (2009)

    Google Scholar 

  14. Petit, E., Bodin, F., Papaure, G., Dru, F.: Astex: A hot path based thread extractor for distributed memory system on a chip. In: Proceedings of the 2006 ACM/IEEE Conference on Supercomputing. ACM, New York (2006)

    Google Scholar 

  15. Prabhu, M.K., Olukotun, K.: Using thread-level speculation to simplify manual parallelization. In: Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 1–12. ACM, New York (2003)

    Google Scholar 

  16. Quiñones, C.G., Madriles, C., Sánchez, J., Marcuello, P., González, A., Tullsen, D.M.: Mitosis compiler: An infrastructure for speculative threading based on pre-computation slices. In: Proceedings of the 2005 ACM SIGPLAN Conference on Programming Language Design and Implementation, pp. 269–279. ACM, New York (2005)

    Chapter  Google Scholar 

  17. Renau, J., Tuck, J., Liu, W., Ceze, L., Strauss, K., Torrellas, J.: Tasking with out-of-order spawn in tls chip multiprocessors: Microarchitecture and compilation. In: Proceedings of the 19th Annual International Conference on Supercomputing, pp. 179–188. ACM, New York (2005)

    Chapter  Google Scholar 

  18. Sarangi, S.R., Torrellas, J., Liu, W., Zhou, Y.: Reslice: Selective re-execution of long-retired misspeculated instructions using forward slicing. In: Proceedings of the 38th Annual IEEE/ACM International Symposium on Microarchitecture, pp. 257–270. IEEE Computer Society, Washington, DC (2005)

    Chapter  Google Scholar 

  19. Sohi, G.S., Breach, S.E., Vijaykumar, T.N.: Multiscalar processors. In: Proceedings of the 22Nd Annual International Symposium on Computer Architecture, pp. 414–425. ACM, New York (1995)

    Chapter  Google Scholar 

  20. Steffan, J.G., Colohan, C., Zhai, A., Mowry, T.C.: The stampede approach to thread-level speculation. ACM Transactions Computer Systems 23(3), 253–300 (2005)

    Article  Google Scholar 

  21. Vijaykumar, T.N., Gopal, S., Smith, J., Sohi, G.: Speculative versioning cache. IEEE Transactions on Parallel and Distributed Systems 12(12), 1305–1317 (2001)

    Article  Google Scholar 

  22. Xekalakis, P., Cintra, M.: Handling branches in tls systems with multi-path execution. In: 2010 IEEE 16th International Symposium on High Performance Computer Architecture, pp. 1–12 (2010)

    Google Scholar 

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Li, M., Zhao, Y., Tao, Y. (2014). Dynamically Spawning Speculative Threads to Improve Speculative Path Execution. In: Sun, Xh., et al. Algorithms and Architectures for Parallel Processing. ICA3PP 2014. Lecture Notes in Computer Science, vol 8631. Springer, Cham. https://doi.org/10.1007/978-3-319-11194-0_15

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  • DOI: https://doi.org/10.1007/978-3-319-11194-0_15

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-11193-3

  • Online ISBN: 978-3-319-11194-0

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