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International Conference on Information Security and Cryptology

Inscrypt 2013: Information Security and Cryptology pp 325–342Cite as

Multivariate Leakage Model for Improving Non-profiling DPA on Noisy Power Traces

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Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 8567))

Abstract

Profiling power attacks like Template attack and Stochastic attack optimize their performance by jointly evaluating the leakages of multiple sample points. However, such multivariate approaches are rare among non-profiling Differential Power Analysis (DPA) attacks, since integration of the leakage of a higher SNR sample point with the leakage of lower SNR sample point might result in a decrease in the overall performance. One of the few successful multivariate approaches is the application of Principal Component Analysis (PCA) for non-profiling DPA. However, PCA also performs sub-optimally in the presence of high noise. In this paper, a multivariate model for an FPGA platform is introduced for improving the performances of non-profiling DPA attacks. The introduction of the proposed model greatly increases the success rate of DPA attacks in the presence of high noise. The experimental results on both simulated power traces and real power traces are also provided as an evidence.

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Acknowledgements

The work described in this paper has been supported in part by Department of Information Technology, India. We also thank Prof. Sylvain Guilley of TELECOM-ParisTech, France for his insightful discussion and suggestion on the work.

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Authors and Affiliations

  1. Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur, India

    Suvadeep Hajra & Debdeep Mukhopadhyay

Authors
  1. Suvadeep Hajra
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  2. Debdeep Mukhopadhyay
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Corresponding author

Correspondence to Suvadeep Hajra .

Editor information

Editors and Affiliations

  1. Chinese Academy of Sciences, Beijing, China

    Dongdai Lin

  2. University of Texas, San Antonio, Texas, USA

    Shouhuai Xu

  3. Columbia University, New York, New York, USA

    Moti Yung

A Experimental Setup and Pre-processing

A Experimental Setup and Pre-processing

For all the experiments, we have used standard side-channel evaluation board SASEBO-GII [11]. It consists of two FPGA device Spartan-3A XC3S400A and Virtex-5 xc5vlx50. Spartan-3A acts as the control FPGA where as Virtex-5 contains the target cryptographic implementation. The cryptographic FPGA is driven by a clock frequency of \(2\) MHz. During the encryption process, voltage drops across VCC and GND of Virtex-5 are captured by Tektronix MSO 4034B Oscilloscope at the rate of \(2.5\) GS/s i.e. \(1,250\) samples per clock period.

The traces acquired using the above setup are already horizontally aligned. However, they are not vertically aligned. The vertical alignment of the traces are performed by subtracting the DC bias from each sample point of the trace. The DC bias of each trace is computed by averaging the leakages of a window taken from a region when no computation is going on. This step is also necessary since the distinguisher Scalar Product is sensitive to the absolute value of mean leakages.

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Hajra, S., Mukhopadhyay, D. (2014). Multivariate Leakage Model for Improving Non-profiling DPA on Noisy Power Traces. In: Lin, D., Xu, S., Yung, M. (eds) Information Security and Cryptology. Inscrypt 2013. Lecture Notes in Computer Science(), vol 8567. Springer, Cham. https://doi.org/10.1007/978-3-319-12087-4_21

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  • DOI: https://doi.org/10.1007/978-3-319-12087-4_21

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-12086-7

  • Online ISBN: 978-3-319-12087-4

  • eBook Packages: Computer ScienceComputer Science (R0)

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