Abstract
To enhance the efficiency and stability of real-time data acquisition and transmission in motion control process, a high-speed real-time communication architecture based on FPGA and DSP is developed in this paper. The direct-memory-access (DMA) control module initiates DMA transfers over the peripheral-component-interconnect (PCI) bus. After that, two first-in-first-out (FIFO) buffers work as caches and convert data widths between the PCI bus and the local bus. Consequently, the data caches can be accessed by DSP over the local bus under DMA mode. The size of data transferred each time is able to be adjusted according to the application requirements. Experiments are carried out to demonstrate that the proposed communication architecture is capable of achieving high speed and stability in data communication with low consumption of compute resources.
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Hu, J., Wang, H., Liu, C., Wu, J., Xiong, Z. (2014). Design and Implementation of High-Speed Real-Time Communication Architecture for PC-Based Motion Control System. In: Zhang, X., Liu, H., Chen, Z., Wang, N. (eds) Intelligent Robotics and Applications. ICIRA 2014. Lecture Notes in Computer Science(), vol 8918. Springer, Cham. https://doi.org/10.1007/978-3-319-13963-0_41
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DOI: https://doi.org/10.1007/978-3-319-13963-0_41
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-13962-3
Online ISBN: 978-3-319-13963-0
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