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International Symposium on Applied Reconfigurable Computing

ARC 2015: Applied Reconfigurable Computing pp 129–140Cite as

SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs

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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 9040))

Abstract

Flash-based Field Programmable Gate Arrays (Flash-based FPGAs) are becoming more and more interesting for safety critical applications due to their re-programmability features while being non-volatile. However, Single Event Transients (SETs) in combinational logic represent their primary source of critical errors since they can propagate and change their shape traversing combinational paths and being broadened and amplified before sampled by sequential Flip-Flops. In this paper the SET sensitivity of circuits implemented in Flash-based FPGAs is mitigated with respect to the working frequency and different FPGA routing architecture. We outline a parametric routing scheme and placement and routing tools based on an iterative partitioning algorithm able to generate high performance circuits by reducing the wires delay and reducing the SET sensitivity. The efficiency of the proposed tools has been evaluated on a Microsemi Flash-based FPGA implementing different benchmark circuits including a RISC microprocessor. Experimental results demonstrated the reduction of SET sensitivity of more than 30% on the average versus state-of-the-art mitigation solutions and a performance improvement of about 10% of the nominal working frequency.

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References

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Author information

Authors and Affiliations

  1. Dipartimento di Automatica e Informatica, CAD Group, Politecnico di Torino, Torino, Italy

    Luca Sterpone & Boyang Du

Authors
  1. Luca Sterpone
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  2. Boyang Du
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Corresponding author

Correspondence to Luca Sterpone .

Editor information

Editors and Affiliations

  1. Tohoku University, Sendai, Japan

    Kentaro Sano

  2. National Technical University of Athens, Athens, Greece

    Dimitrios Soudris

  3. Ruhr-Universität Bochum, Bochum, Germany

    Michael Hübner

  4. University of Southern California, Marina del Rey, California, USA

    Pedro C. Diniz

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© 2015 Springer International Publishing Switzerland

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Sterpone, L., Du, B. (2015). SET-PAR: Place and Route Tools for the Mitigation of Single Event Transients on Flash-Based FPGAs. In: Sano, K., Soudris, D., Hübner, M., Diniz, P. (eds) Applied Reconfigurable Computing. ARC 2015. Lecture Notes in Computer Science(), vol 9040. Springer, Cham. https://doi.org/10.1007/978-3-319-16214-0_11

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  • DOI: https://doi.org/10.1007/978-3-319-16214-0_11

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-16213-3

  • Online ISBN: 978-3-319-16214-0

  • eBook Packages: Computer ScienceComputer Science (R0)

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