Abstract
Although FPGAs have the potential to bring software-like flexibility and agility to the hardware world, designing for FPGAs remains a difficult task divorced from standard software engineering norms. A better programming flow would go far towards realizing the potential of widely deployed, programmable hardware. We propose a general methodology based on domain specific languages embedded in the functional language Haskell to bridge the gap between high level abstractions that support programmer productivity and the need for high performance in FPGA circuit implementations. We illustrate this methodology with a framework for regular expression to hardware compilers, written in Haskell, that supports high programmer productivity while producing circuits whose performance matches and, indeed, exceeds that of a state of the art, hand-optimized VHDL-based tool. For example, after applying a novel optimization pass, throughput increased an average of \(28.3\,\%\) over the state of the art tool for one set of benchmarks. All code discussed in the paper is available online [1].
This Research Was Supported by the Office of the Assistant Secretary of Defense for Research and Engineering, the U.S. Department of Education Under GAANN Grant Number P200A100053, NSF CAREER Award 00017806, and NSF Award CNS-1319748.
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Graves, I., Procter, A., Harrison, W.L., Becchi, M., Allwein, G. (2015). Hardware Synthesis from Functional Embedded Domain-Specific Languages: A Case Study in Regular Expression Compilation. In: Sano, K., Soudris, D., Hübner, M., Diniz, P. (eds) Applied Reconfigurable Computing. ARC 2015. Lecture Notes in Computer Science(), vol 9040. Springer, Cham. https://doi.org/10.1007/978-3-319-16214-0_4
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