Abstract
The objective of the paper is to introduce a new approach to the evolutionary design of digital circuits conducted directly at transistor level. In order to improve the time consuming evaluation of candidate solutions, a discrete event-driven simulator was introduced. The proposed simulator operates on multiple logic levels to achieve reasonable trade-off between performance and precision. A suitable level of abstraction reflecting the behaviour of real MOSFET transistors is utilized to minimize the production of incorrectly working circuits. The proposed approach is evaluated in evolution of basic logic circuits having more than 20 transistors. The goal of an evolutionary algorithm is to design a circuit having the minimal number of transistors and exhibiting the minimal delay. In addition to that, various parameter settings are investigated to increase the success rate of the evolutionary design.
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Kapre, N., DeHon, A.: Accelerating spice model-evaluation using fpgas. In: 17th IEEE Symposium on Field Programmable Custom Computing Machines, FCCM 2009, pp. 37–44, April 2009
Miller, J.F. (ed.): Cartesian Genetic Programming. Natural Computing Series, 22nd edn. Springer, Berlin (2011)
Miller, J.F., Job, D., Vassilev, V.K.: Principles in the evolutionary design of digital circuits - Part I. Genet. Program. Evolvable Mach. 1(1), 8–35 (2000)
Miller, J.F., Job, D., Vassilev, V.K.: Principles in the evolutionary design of digital circuits - Part II. Genet. Program. Evolvable Mach. 1(3), 259–288 (2000)
Shams, A., Bayoumi, M.: A novel high-performance cmos 1-bit full-adder cell. IEEE Trans. Circ. Syst. II: Analog Digit. Signal Process. 47(5), 478–481 (2000)
Trefzer, M.: Evolution of transistor circuits. Ph.D. thesis, Ruprecht-Karls-Universitt Heidelberg (2006)
Vassilev, V., Job, D., Miller, J.: Towards the automatic design of more efficient digital circuits. In: Proceedings of the 2nd NASA/DoD Workshop on Evolvable Hardware, pp. 151–160. IEEE Computer Society, Los Alamitos (2000)
Walker, J.A., Hilder, J.A., Tyrrell, A.M.: Evolving variability-tolerant CMOS designs. In: Hornby, G.S., Sekanina, L., Haddow, P.C. (eds.) ICES 2008. LNCS, vol. 5216, pp. 308–319. Springer, Heidelberg (2008)
Walker, M., Edwards, H., Messom, C.H.: Success effort and other statistics for performance comparisons in genetic programming. In: IEEE Congress on Evolutionary Computation, pp. 4631–4638 (2007)
Weste, N.H., Harris, D.: CMOS VLSI Design: A Circuits and Systems Perspective, 3rd edn. Addison-Wesley, Boston (2005)
Žaloudek, L., Sekanina, L.: Transistor-level evolution of digital circuits using a special circuit simulator. In: Hornby, G.S., Sekanina, L., Haddow, P.C. (eds.) ICES 2008. LNCS, vol. 5216, pp. 320–331. Springer, Heidelberg (2008)
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This work was supported by the Czech science foundation project 14-04197S.
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Mrazek, V., Vasicek, Z. (2015). Evolutionary Design of Transistor Level Digital Circuits Using Discrete Simulation. In: Machado, P., et al. Genetic Programming. EuroGP 2015. Lecture Notes in Computer Science(), vol 9025. Springer, Cham. https://doi.org/10.1007/978-3-319-16501-1_6
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DOI: https://doi.org/10.1007/978-3-319-16501-1_6
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