Abstract
Reducing power dissipation without performance degradation is one of the most important issues for all computing systems, such as supercomputers, cloud servers, desktop PCs, medical systems, smart-phones and wearable devices. Exploiting parallelism, careful frequency-and-voltage control and clock-and-power-gating control for multicore/manycore systems are promising to attain performance improvements and reducing power dissipation. However, the hand parallelization and power reduction of application programs are very difficult and time-consuming. The OSCAR automatic parallelization compiler has been developed to overcome these problems by realizing automatic low-power control in addition to the parallelization. This paper evaluates performance of the low-power control technology of the OSCAR compiler on Intel Haswell and ARM multicore platforms. The evaluations show that the power consumption is reduced to 2/5 using 3 cores on the Intel Haswell multicore for the H.264 decoder and 1/3 for Optical Flow on 3 cores with the power control compared with 3 cores without power control. On the ARM Cortex-A9 using 3 cores, the power control reduces power consumption to 1/2 with the H.264 decoder and 1/3 with Optical Flow. These show that the OSCAR multi-platform compiler allows us to reduce the power consumption on Intel and ARM multicores.
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NVIDIA Corporation: White paper NVIDIA Tegra: Multi-processor Architecture. (2010)
ARM:Jeff, B.: Advances in big.LITTLE Technology for Power and Energy Savings. Write paper, 1–11 (2012)
Kurd, N., Chowdhury, M., Burton, E., Thomas, T.P., Mozak, C., Boswell, B., Lal, M., Deval, A., Douglas, J., Elassal, M., Nalamalpu, A., Wilson, T.M., Merten, M., Chennupaty, S., Gomes, W., Kumar, R.: Haswell: A family of IA 22nm processors. In: Solid-State Circuits Conference Digest of Technical Papers, pp. 112–113 (2014)
OpenMP. http://openmp.org/
Kasahara, H., Obata, M., Ishizaka, K.: Automatic coarse grain task parallel processing on SMP using openMP. In: Midkiff, S.P., Moreira, J.E., Gupta, M., Chatterjee, S., Ferrante, J., Prins, J.F., Pugh, B., Tseng, C.-W. (eds.) LCPC 2000. LNCS, vol. 2017, pp. 189–207. Springer, Heidelberg (2001)
Obata, M., Shirako, J., Kaminaga, H., Ishizaka, K., Kasahara, H.: Hierarchical parallelism control for multigrain parallel processing. In: Pugh, B., Tseng, C.-W. (eds.) LCPC 2002. LNCS, vol. 2481, pp. 31–44. Springer, Heidelberg (2005)
Kimura, K., Mase, M., Mikami, H., Miyamoto, T., Shirako, J., Kasahara, H.: OSCAR API for real-time low-power multicores and its performance on multicores and SMP servers. In: Gao, G.R., Pollock, L.L., Cavazos, J., Li, X. (eds.) LCPC 2009. LNCS, vol. 5898, pp. 188–202. Springer, Heidelberg (2010)
Honda, H., Kasahara, H.: Coarse grain parallelism detection scheme of a fortran program. Syst. Comput. Jpn. 22, 24–36 (1991)
Shirako, J., Oshiyama, N., Wada, Y., Shikano, H., Kimura, K., Kasahara, H.: Compiler control power saving scheme for multi core processors. In: Ayguadé, E., Baumgartner, G., Ramanujam, J., Sadayappan, P. (eds.) LCPC 2005. LNCS, vol. 4339, pp. 362–376. Springer, Heidelberg (2006)
Shirako, J., Yoshida, M., Oshiyama, N., Wada, Y., Nakano, H., Shikano, H., Kimura, K., Kasahara, H.: Performance evaluation of compiler controlled power saving scheme. In: Labarta, J., Joe, K., Sato, T. (eds.) ISHPC 2006 and ALPS 2006. LNCS, vol. 4759, pp. 480–493. Springer, Heidelberg (2008)
Intel: Mobile 4th Generation Intel Core Processor Family, Mobile Intel Pentium Processor Family, and Mobile Intel Celeron Processor Family. Datasheet - vol. 1 of 2 (2014)
CPU hotplug Support in Linux(tm) Kernel. https://www.kernel.org/doc/Documentation/cpu-hotplug.txt
ARM Corporation: Cortex-A9 Technical Reference Manual. http://infocenter.arm.com/help/topic/com.arm.doc.ddi0388i/DDI0388I_cortex_a9_r4p1_trm.pdf
Google: Android Developers. http://developer.android.com/index.html
Yamamoto, H., et al.: OSCAR compiler controlled multicore power reduction on android platform. In: Caṣcaval, C., Montesinos-Ortego, P. (eds.) LCPC 2013 - Testing. LNCS, vol. 8664, pp. 155–168. Springer, Heidelberg (2014)
ODROID-X2. http://www.hardkernel.com/renewal2011/products/prdtinfo.php?gcode=G135235611947
Samsung Electronics: White Paper of Exynos 5 (2011)
Samsung Electronics: Samsung Exynos 4 Quad (Exynos 4412) RISC Microprocessor User’s Manual (2012)
Samsung Semiconductors Global Site. https://www.samsung.com/global/business/semiconductor/product/poweric/overview
GPIO Interfaces. https://www.kernel.org/doc/Documentation/gpio.txt
Lee, C., Potkonjak, M., Mangione-Smith, W.: MediaBench: a tool for evaluating and synthesizing multimedia and communications systems. In: Proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture, pp. 330–335 (1997)
Opencv. http://www.opencv.org
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Hirano, T. et al. (2015). Evaluation of Automatic Power Reduction with OSCAR Compiler on Intel Haswell and ARM Cortex-A9 Multicores. In: Brodman, J., Tu, P. (eds) Languages and Compilers for Parallel Computing. LCPC 2014. Lecture Notes in Computer Science(), vol 8967. Springer, Cham. https://doi.org/10.1007/978-3-319-17473-0_16
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DOI: https://doi.org/10.1007/978-3-319-17473-0_16
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