Abstract
Enhancing electronic circuits with ad hoc testing circuitry—so-called Design for Test (DFT)—is a technique that enables one to thoroughly test circuits after production. But this insertion of new elements itself may sometimes be a challenge, for bad choices could lead to unacceptable degradations of features of the circuit, while good choices may help reduce testing costs and circuit production costs. This chapter demonstrates how methods from Operations Research—a scientific discipline rooted in both mathematics and computer science, leaning strongly on the formal modeling of optimization issues—help us adress such challenges and build efficient solutions leading to real-world solutions that may be integrated into electronic design software tools.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Aktouf, C., Fleury, H., Robach, C.: Inserting scan at the behavorial level. IEEE Des. Test Comput. 17, 34–42 (2000)
Asaka, T., Bhattacharya, S., Dey, S., Yoshida, M.: H-SCAN+: a practical low-overhead RTL design-for-testability technique for industrial designs. In: Proceedings of ITC (1997)
Benso, A., Di Carlo, S., Di Natale, G., Prinetto, P., Lobetti Bodoni, M.: A programmable BIST architecture for clusters of multiple-port srams. In: Proceedings of International Test Conference, pp. 557–566 (2000). doi:10.1109/TEST.2000.894249
Bhattacharya, S., Dey, S.: H-SCAN: a high level alternative to full-scan testing with reduced area and test application overheads. In: Proceedings of VLSI Test Symposium (1996)
Fonseca, C., Fleming, P.: An overview of evolutionary algorithms in multiobjective optimization. Evol. Comput. 3(1), 1–16 (1995). doi:10.1162/evco.1995.3.1.1
Huang, Y., Tsai, C.C., Mukherjee, N., Samman, O., Cheng, W.T., Reddy, S.M.: Synthesis of scan chains for netlist descriptions at RT-level. J. Electron. Test. 18(2), 189–201 (2002)
Mazumder, P., Chakraborty, K.: Testing and Testable Design of High-Density Random-Access Memories, vol. 6. Springer, Boston (1996)
Miyazaki, M., Yoneda, T., Fujiwara, H.: A memory grouping method for sharing memory BIST logic. In: Asia and South Pacific Conference on Design Automation, 6 p. (2006). doi:10.1109/ASPDAC.2006.1594763
Roy, S.: RTL based scan BIST. In: Proceedings of VHDL International User’s Forum (VIUF) (1997)
Wang, L.T., Wu, C.W., Wen, X.: VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon). Morgan Kaufmann Publishers Inc., San Francisco (2006)
Zaourar, L., Chentoufi, J., Kieffer, Y., Wenzel, A., Grandvaux, F.: A shared BIST optimization methodology for memory test. In: 15th IEEE European Test Symposium (ETS), p. 255 (2010). doi:10.1109/ETSYM.2010.5512736
Zaourar, L., Kieffer, Y., Aktouf, C.: An innovative methodology for scan chain insertion and analysis at RTL. In: 20th Asian Test Symposium (ATS), pp. 66–71 (2011). doi:10.1109/ATS.2011.20
Zaourar, L., Kieffer, Y., Aktouf, C.: A graph-based approach to optimal scan chain stitching using RTL design descriptions. In: VLSI Design (2012). doi:10.1155/2012/312808
Zaourar, L., Kieffer, Y., Wenzel, A.: A complete methodology for determining memory BIST optimization under wrappers sharing constraints. In: 3rd Asia Symposium on Quality Electronic Design (ASQED), pp. 46–53 (2011). doi:10.1109/ASQED.2011.6111701
Zaourar, L., Kieffer, Y., Wenzel, A.: A multi-objective optimization for memory BIST sharing using a genetic algorithm. In: IEEE 17th International On-Line Testing Symposium (IOLTS), pp. 73–78 (2011). doi:10.1109/IOLTS.2011.5993814
Zorian, Y.: A distributed BIST control scheme for complex VLSI devices. In: Eleventh Annual IEEE VLSI Test Symposium, Digest of Papers, pp. 4–9 (1993). doi:10.1109/VTEST.1993.313316
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2015 Springer International Publishing Switzerland
About this chapter
Cite this chapter
Kieffer, Y., Zaourar, L. (2015). Applying Operations Research to Design for Test Insertion Problems. In: Fakhfakh, M., Tlelo-Cuautle, E., Siarry, P. (eds) Computational Intelligence in Digital and Network Designs and Applications. Springer, Cham. https://doi.org/10.1007/978-3-319-20071-2_6
Download citation
DOI: https://doi.org/10.1007/978-3-319-20071-2_6
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-20070-5
Online ISBN: 978-3-319-20071-2
eBook Packages: Computer ScienceComputer Science (R0)