Abstract
VLSI architectures for finding the first W maximum/minimum values are highly demanded in the fields of K-best MIMO detector, non-binary LDPC decoder and product-code decoder. In this paper, a VLSI architecture based on parallel comparing scheme is explored for finding the first W maximum/minimum values from M inputs. The place and route results using a TSMC 90-nm CMOS technology show that, despite some hardware cost, it achieves on average a 3.6x faster speed performance compared to the existing partial sorting architectures.
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Xiao, G., Ahmad, W., Zaidi, S.A.A., Roch, M.R., Causapruno, G. (2016). High Speed VLSI Architecture for Finding the First W Maximum/Minimum Values. In: De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. Lecture Notes in Electrical Engineering, vol 351. Springer, Cham. https://doi.org/10.1007/978-3-319-20227-3_5
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DOI: https://doi.org/10.1007/978-3-319-20227-3_5
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