Skip to main content
SpringerLink
Log in
Book cover

International Conference on Cryptology in India

INDOCRYPT 2015: Progress in Cryptology -- INDOCRYPT 2015 pp 329–346Cite as

BitCryptor: Bit-Serialized Flexible Crypto Engine for Lightweight Applications

  • Conference paper
  • First Online:

  • 1101 Accesses

Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 9462))

Abstract

There is a significant effort in building lightweight cryptographic operations, yet the proposed solutions are typically single-purpose modules that can implement a single functionality. In contrast, we propose BitCryptor, a multi-purpose, compact processor for cryptographic applications on reconfigurable hardware. The proposed crypto engine can perform pseudo-random number generation, strong collision-resistant hashing and variable-key block cipher encryption. The hardware architecture utilizes SIMON, a recent lightweight block cipher, as its core. The complete engine uses a bit-serial design methodology to minimize the area. Implementation results on the Xilinx Spartan-3 s50 FPGA show that the proposed architecture occupies 95 slices (187 LUTs, 102 registers), which is 10\(\times \) smaller than the nearest comparable multi-purpose design. BitCryptor is also smaller than the majority of recently proposed lightweight single-purpose designs. Therefore, it is a very efficient cryptographic IP block for resource-constrained domains, providing a good performance at a minimal area overhead.

This is a preview of subscription content, log in via an institution.

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Notes

  1. 1.

    The previous work implements a 128-bit security encryption with a fixed key, results section elaborates on comparisons.

References

  1. Abed, F., List, E., Lucks, S., Wenzel, J.: Differential and linear cryptanalysis of reduced-round SIMON. Cryptology ePrint Archive, Report 2013/526 (2013). http://eprint.iacr.org/

  2. Adas, M.: On the FPGA based implementation of SPONGENT (2011)

    Google Scholar 

  3. Alkhzaimi, H.A., Lauridsen, M.M.: Cryptanalysis of the SIMON family of block ciphers. Cryptology ePrint Archive, Report 2013/543 (2013)

    Google Scholar 

  4. Andraka, R.J.: Building a high performance bit-serial processor in an FPGA. In: Proceedings of Design SuperCon., vol. 96, pp. 1–5 (1996)

    Google Scholar 

  5. Aysu, A., Gulcan, E., Schaumont, P.: SIMON says: break area records of block ciphers on FPGAs. IEEE Embed. Syst. Lett. 6(2), 37–40 (2014)

    Article  Google Scholar 

  6. Beaulieu, R., Shors, D., Smith, J., Treatman-Clark, S., Weeks, B., Wingers, L.: The SIMON and SPECK families of lightweight block ciphers. Cryptology ePrint Archive, Report 2013/404 (2013). http://eprint.iacr.org/

  7. Bogdanov, A.A., Knudsen, L.R., Leander, G., Paar, C., Poschmann, A., Robshaw, M., Seurin, Y., Vikkelsoe, C.: PRESENT: an ultra-lightweight block cipher. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 450–466. Springer, Heidelberg (2007). http://dx.doi.org/10.1007/978-3-540-74735-2_31

    Chapter  Google Scholar 

  8. Bossuet, L., Grand, M., Gaspar, L., Fischer, V., Gogniat, G.: Architectures of flexible symmetric key crypto engines-a survey: from hardware coprocessor to multi-crypto-processor system on chip. ACM Comput. Surv. 45(4), 41:1–41:32 (2013). http://doi.acm.org/10.1145/2501654.2501655

    Article  Google Scholar 

  9. Chapman, K.: Picoblaze 8-bit microcontroller for virtex-e and spartan-ii/iie devices. Xilinx Application Notes (2003)

    Google Scholar 

  10. Chaves, R.: Compact CLEFIA implementation on FPGAs. In: Athanas, P., Pnevmatikatos, D., Sklavos, N. (eds.) Embedded Systems Design with FPGAs, pp. 225–243. Springer, New York (2013). http://dx.doi.org/10.1007/978-1-4614-1362-2_10

    Chapter  Google Scholar 

  11. Chu, J., Benaissa, M.: Low area memory-free FPGA implementation of the AES algorithm. In: 2012 22nd International Conference on Field Programmable Logic and Applications (FPL), pp. 623–626, August 2012

    Google Scholar 

  12. Clark, J.A., Jacob, J.L.: A survey of authentication protocol literature: Version 1.0 (1997)

    Google Scholar 

  13. De Cannière, C.: Trivium: a stream cipher construction inspired by block cipher design principles. In: Katsikas, S.K., López, J., Backes, M., Gritzalis, S., Preneel, B. (eds.) ISC 2006. LNCS, vol. 4176, pp. 171–186. Springer, Heidelberg (2006). http://dx.doi.org/10.1007/11836810_13

    Chapter  Google Scholar 

  14. Dinu, D., Corre, Y.L., Khovratovich, D., Perrin, L., Groschdl, J., Biryukov, A.: Triathlon of lightweight block ciphers for the internet of things. Cryptology ePrint Archive, Report 2015/209 (2015). http://eprint.iacr.org/

  15. Ferguson, N., Schneier, B.: Practical Cryptography. Wiley, New York (2003). http://books.google.com/books?id=7SiKtxPrrRMC

    Google Scholar 

  16. Girard, O.: openmsp430 (2009)

    Google Scholar 

  17. Good, T., Benaissa, M.: AES on FPGA from the fastest to the smallest. In: Rao, J.R., Sunar, B. (eds.) CHES 2005. LNCS, vol. 3659, pp. 427–440. Springer, Heidelberg (2005)

    Chapter  Google Scholar 

  18. Gulcan, E., Aysu, A., Schaumont, P.: A flexible and compact hardware architecture for the SIMON block cipher. In: Eisenbarth, T., Öztürk, E. (eds.) LightSec 2014. LNCS, vol. 8898, pp. 34–50. Springer, Heidelberg (2015)

    Google Scholar 

  19. Guo, J., Peyrin, T., Poschmann, A.: The PHOTON family of lightweight hash functions. In: Rogaway, P. (ed.) CRYPTO 2011. LNCS, vol. 6841, pp. 222–239. Springer, Heidelberg (2011). http://dx.doi.org/10.1007/978-3-642-22792-9_13

    Chapter  Google Scholar 

  20. Hirose, S.: Some plausible constructions of double-block-length hash functions. In: Robshaw, M. (ed.) FSE 2006. LNCS, vol. 4047, pp. 210–225. Springer, Heidelberg (2006)

    Chapter  Google Scholar 

  21. Hwang, D., Chaney, M., Karanam, S., Ton, N., Gaj, K.: Comparison of FPGA-targeted hardware implementations of eSTREAM stream cipher candidates. In: State of the Art of Stream Ciphers Workshop, SASC 2008, Lausanne, Switzerland, pp. 151–162, February 2008

    Google Scholar 

  22. Kaps, J.-P.: Chai-tea, cryptographic hardware implementations of xTEA. In: Chowdhury, D.R., Rijmen, V., Das, A. (eds.) INDOCRYPT 2008. LNCS, vol. 5365, pp. 363–375. Springer, Heidelberg (2008)

    Chapter  Google Scholar 

  23. Kaps, J., Yalla, P., Surapathi, K.K., Habib, B., Vadlamudi, S., Gurung, S.: Lightweight implementations of SHA-3 finalists on FPGAs. In: The Third SHA-3 Candidate Conference (2012)

    Google Scholar 

  24. Laue, R., Kelm, O., Schipp, S., Shoufan, A., Huss, S.: Compact AES-based architecture for symmetric encryption, hash function, and random number generation. In: International Conference on Field Programmable Logic and Applications, FPL 2007, pp. 480–484, August 2007

    Google Scholar 

  25. Liu, S., Xiang, L., Xu, J., Li, X.: Intelligent engine room IoT system based on multi-processors. Microelectron. Comput. 9, 049 (2011)

    Google Scholar 

  26. Mace, F., Standaert, F.X., Quisquater, J.J.: FPGA implementation(s) of a scalable encryption algorithm. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 16(2), 212–216 (2008)

    Article  Google Scholar 

  27. Menezes, A.J., Van Oorschot, P.C., Vanstone, S.A.: Handbook of Applied Cryptography. CRC Press, Boca Raton (2010)

    Google Scholar 

  28. Nalla-Anandakumar, N., Peyrin, T., Poschmann, A.: A very compact FPGA implementation of LED and PHOTON. In: Meier, W., Mukhopadhyay, D. (eds.) INDOCRYPT 2014. LNCS, vol. 8885, pp. 304–321. Springer, Heidelberg (2014). http://dx.doi.org/10.1007/978-3-319-13039-2_18

    Google Scholar 

  29. Paul, G., Chattopadhyay, A.: Three snakes in one hole: the first systematic hardware accelerator design for sosemanuk with optional serpent and snow 2.0 modes. IEEE Trans. Comput. PP(99), 1–1 (2015)

    Article  Google Scholar 

  30. De la Piedra, A., Braeken, A., Touhafi, A.: Sensor systems based on FPGAs and their applications: a survey. Sensors 12(9), 12235–12264 (2012)

    Article  Google Scholar 

  31. Plessl, C., Enzler, R., Walder, H., Beutel, J., Platzner, M., Thiele, L.: Reconfigurable hardware in wearable computing nodes. In: Proceedings of the Sixth International Symposium on Wearable Computers, ISWC 2002, pp. 215–222. IEEE (2002)

    Google Scholar 

  32. Rukhin, A., Soto, J., Nechvatal, J., Smid, M., Barker, E.: A statistical test suite for random and pseudorandom number generators for cryptographic applications. Technical report, DTIC Document (2001)

    Google Scholar 

  33. Sayilar, G., Chiou, D.: Cryptoraptor: high throughput reconfigurable cryptographic processor. In: Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2014, pp. 154–161. IEEE Press, Piscataway (2014). http://dl.acm.org/citation.cfm?id=2691365.2691398

  34. Sen Gupta, S., Chattopadhyay, A., Khalid, A.: Designing integrated accelerator for stream ciphers with structural similarities. Crypt. Commun. 5(1), 19–47 (2013). http://dx.doi.org/10.1007/s12095-012-0074-6

    Article  MATH  MathSciNet  Google Scholar 

  35. Shahzad, K., Khalid, A., Rakossy, Z., Paul, G., Chattopadhyay, A.: Coarx: a coprocessor for arx-based cryptographic algorithms. In: 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC), pp. 1–10, May 2013

    Google Scholar 

  36. Smart, N., Babbage, S., Catalano, D., Cid, C., de Weger, B., Dunkelman, O., Ward, M.: ECRYPT II yearly report on algorithms and keysizes (2011–2012). European Network of Excellence in Cryptology (ECRYPT II), September 2012

    Google Scholar 

  37. Standaert, F.X., Piret, G., Rouvroy, G., Quisquater, J.J.: FPGA implementations of the ICEBERG block cipher. In: International Conference on Information Technology: Coding and Computing, ITCC 2005, vol. 1, pp. 556–561 (2005)

    Google Scholar 

  38. Wang, Q., Liu, Z., Varıcı, K., Sasaki, Y., Rijmen, V., Todo, Y.: Cryptanalysis of reduced-round SIMON32 and SIMON48. In: Meier, W., Mukhopadhyay, D. (eds.) INDOCRYPT 2014. LNCS, vol. 8885, pp. 143–160. Springer, Heidelberg (2014)

    Google Scholar 

  39. Winternitz, R.S.: A secure one-way hash function built from DES. In: 2012 IEEE Symposium on Security and Privacy, p. 88. IEEE Computer Society (1984)

    Google Scholar 

  40. Yalla, P., Kaps, J.: Compact FPGA implementation of CAMELLIA. In: International Conference on Field Programmable Logic and Applications, FPL 2009, pp. 658–661 (2009)

    Google Scholar 

  41. Yalla, P., Kaps, J.: Lightweight cryptography for FPGAs. In: International Conference on Reconfigurable Computing and FPGAs, ReConFig 2009, pp. 225–230 (2009)

    Google Scholar 

  42. Yang, G., Zhu, B., Suder, V., Aagaard, M.D., Gong, G.: The SIMECK family of lightweight block ciphers. In: Güneysu, T., Handschuh, H. (eds.) CHES 2015. LNCS, vol. 9293, pp. 307–329. Springer, Heidelberg (2015). http://dx.doi.org/10.1007/978-3-662-48324-4_16

    Chapter  Google Scholar 

Download references

Acknowledgements

This project was supported in part by the National Science Foundation grant no 1115839 and 1314598.

Author information

Authors and Affiliations

  1. Secure Embedded Systems, Center for Embedded Systems for Critical Applications, Bradley Department of ECE, Virginia Tech, Blacksburg, VA, 24061, USA

    Ege Gulcan, Aydin Aysu & Patrick Schaumont

Authors
  1. Ege Gulcan
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Aydin Aysu
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Patrick Schaumont
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Aydin Aysu .

Editor information

Editors and Affiliations

  1. Luxembourg, Luxembourg

    Alex Biryukov

  2. Microsoft Research India, Banglore, India

    Vipul Goyal

Rights and permissions

Reprints and permissions

Copyright information

© 2015 Springer International Publishing Switzerland

About this paper

Cite this paper

Gulcan, E., Aysu, A., Schaumont, P. (2015). BitCryptor: Bit-Serialized Flexible Crypto Engine for Lightweight Applications. In: Biryukov, A., Goyal, V. (eds) Progress in Cryptology -- INDOCRYPT 2015. INDOCRYPT 2015. Lecture Notes in Computer Science(), vol 9462. Springer, Cham. https://doi.org/10.1007/978-3-319-26617-6_18

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-26617-6_18

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-26616-9

  • Online ISBN: 978-3-319-26617-6

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics

Search

Navigation