Abstract
The high scalability of the NoC (network-on-chip) makes it one of the best choices to meet the demand for bandwidth increasing in systems-on-chips and chip multiprocessors. However, the NoC is increasingly becoming power-constrained. A significant part of the NoC’s power is consumed in the router buffer. In this paper, we propose HVCRouter, a novel NoC router design with heterogeneous virtual channels. In particular, HVCRouter incorporates a bufferless channel to respect its power efficiency at low network load. HVCRouter employs a fine-grained power gating algorithm which exploits power saving opportunities at both channel and buffer levels simultaneously, and is able to achieve high power efficiency without degrading performance at varying network utilization. Our experimental results on both synthetic and real workloads show that HVCRouter delivers similar performance with FlexiBuffer, the best in the literature. More importantly, HVCRouter consumes an average of 22.797 % less power, and results in 20.698 % lower EDP (energy delay product) than FlexiBuffer.
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Acknowledgments
We thank the anonymous reviewers for their precious feedback. We gratefully acknowledge members of Tianhe interconnect group at NUDT for many inspiring conversations early in the project. The work was partially supported by 863 Program under Grant No. 2012AA01A301, NSFC under Grant No. 61370018, 61272482, and FANEDD under Grant No. 201450.
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Wu, J., Liao, X., Dong, D., Wang, L., Li, C. (2015). HVCRouter: Energy Efficient Network-on-Chip Router with Heterogeneous Virtual Channels. In: Wang, G., Zomaya, A., Martinez, G., Li, K. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2015. Lecture Notes in Computer Science(), vol 9528. Springer, Cham. https://doi.org/10.1007/978-3-319-27119-4_14
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