Note on Fast Bridge Fault Test Generation Based on Critical Area

Abstract

Shrinking feature size and higher integration on semiconductor device manufacturing technology bring a problem of the gap between the defect level estimated at the design stage from the reported one for fabricated devices. As one possible strategy to accurately estimate the defect level, authors have proposed weighted bridge fault coverage estimation. In this study we evaluate the effectiveness of prioritization of target faults based on critical area, aiming to develop fast and compact test pattern set generation. The proposed scheme apply two-step test pattern generation, where test pattern reordering is only applied to the second pattern set which is generated for the residual faults of first small pattern set. The experimental results indicate the proposed scheme can reduce execution time of pattern reordering significantly, while keeping the number of required patterns with the same level as conventional greedy algorithm. We further discuss on test pattern selection algorithm based on only fault detection information, in order to keep the execution time by the linear order with the number of target faults.