Abstract
Due to raising system complexity and higher “time to market” demands in industry, hardware development for fast image processing applications is becoming more and more important. In order to ease and accelerate the design flow, special frameworks aim to hide the HDL code from the developer. On the one hand, many frameworks generate HDL code from a programming language like C++ to synthesize hardware from a higher abstraction level. On the other hand, HDL libraries, which instantiate predefined hardware components, are utilized. In contrast to high level synthesis, hardware designs, resulting from such a library, will lead to resource utilizations close to hand written implementations. Therefore, we propose a library of highly configurable IP blocks and demonstrate how they can be used on different Altera and Xilinx FPGAs. Our blocks are designed in a generic way, which makes the design very flexible in several functional parameters. At the current stage of our block library, it is possible to synthesize hardware for common local operations like Sobel, Laplacian or Median filter, but also complex operations like stereo matching and Canny edge detector. Moreover, we designed an XML based language interface, that gives users, who have only low specific hardware knowledge, access to predefined filter operations. With these features a rapid implementation of image processing operators for FPGA designs becomes possible.
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Acknowledgment
This work was financially supported by the Research Training Group 1773 “Heterogeneous Image Systems”, funded by the German Research Foundation (DFG).
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Häublein, K., Hartmann, C., Reichenbach, M., Fey, D. (2016). Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks. In: Bonato, V., Bouganis, C., Gorgon, M. (eds) Applied Reconfigurable Computing. ARC 2016. Lecture Notes in Computer Science(), vol 9625. Springer, Cham. https://doi.org/10.1007/978-3-319-30481-6_24
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DOI: https://doi.org/10.1007/978-3-319-30481-6_24
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