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Sparse Matrix Multiplication on Dataflow Engines

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Parallel Processing and Applied Mathematics (PPAM 2015)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 9573))

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Abstract

In this paper, a novel architecture for sparse matrix multiplication is proposed. The architecture is suitable for implementation in specific environments such as dataflow engines. In order to avoid multiple streaming of elements from the host, we propose the architecture which buffers the elements from the input stream in on-chip memory in the form of pages. In the case of sparse matrices, the architecture processes only pages with non-zero elements. The proposed architecture allows replication of its blocks in order to parallelize the computation. The architecture is implemented on Maxeler dataflow engine based on Virtex 5 FPGA. The implementation results are given.

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References

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Acknowledgment

The research was supported in part by the Serbian Ministry of Education, Science and Technological Development (Project TR32012).

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Authors and Affiliations

  1. Faculty of Electronic Engineering, University of Nis, Aleksandra Medvedeva 14, P.O. Box 14, 18000, Nis, Serbia

    Vladimir Simic, Vladimir Ciric, Nikola Savic & Ivan Milentijevic

Authors
  1. Vladimir Simic
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  2. Vladimir Ciric
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  3. Nikola Savic
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  4. Ivan Milentijevic
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Corresponding author

Correspondence to Vladimir Simic .

Editor information

Editors and Affiliations

  1. Czestochowa University of Technolog, Czestochowa, Poland

    Roman Wyrzykowski

  2. Department of Computer Science, University of Southern California, Marina Del Rey, California, USA

    Ewa Deelman

  3. Electrical Engineering & Comput. Science, University of Tennessee, Knoxville, Tennessee, USA

    Jack Dongarra

  4. Czestochowa University of Technology, Institute of Computer & Information Sci., Czestochowa, Poland

    Konrad Karczewski

  5. Department of Computer Science, AGH University of Science and Technology, Krakow, Poland

    Jacek Kitowski

  6. Systèmes d’informations, Big Data et Rec, AGH University of Science and Technology, Krakow, Poland

    Kazimierz Wiatr

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© 2016 Springer International Publishing Switzerland

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Simic, V., Ciric, V., Savic, N., Milentijevic, I. (2016). Sparse Matrix Multiplication on Dataflow Engines. In: Wyrzykowski, R., Deelman, E., Dongarra, J., Karczewski, K., Kitowski, J., Wiatr, K. (eds) Parallel Processing and Applied Mathematics. PPAM 2015. Lecture Notes in Computer Science(), vol 9573. Springer, Cham. https://doi.org/10.1007/978-3-319-32149-3_3

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  • DOI: https://doi.org/10.1007/978-3-319-32149-3_3

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-32148-6

  • Online ISBN: 978-3-319-32149-3

  • eBook Packages: Computer ScienceComputer Science (R0)

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