Abstract
We present a more concise formulation of the transformation based synthesis approach for reversible logic synthesis, which is one of the most prominent explicit ancilla-free synthesis approaches. Based on this formulation we devise a symbolic variant of the approach that allows one to find a circuit in shorter time using less memory for the function representation. We present both a BDD based and a SAT based implementation of the symbolic variant. Experimental results show that both approaches are significantly faster than the state-of-the-art method. We were able to find ancilla-free circuit realizations for large optimally embedded reversible functions for the first time.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Notes
- 1.
We also tried to write F to an AIG, perform circuit optimization, and obtain the CNF from the optimized AIG, however, no improvement in runtime could be observed, although the number of clauses can be decreased this way.
- 2.
The code can be downloaded at https://www.github.com/msoeken/cirkit. Check the file addons/cirkit-addon-reversible/demo.cs for a usage demonstration.
References
Alhagi, N., Hawash, M., Perkowski, M.A.: Synthesis of reversible circuits with no ancilla bits for large reversible functions specified with bit equations. In: ISMVL, pp. 39–45 (2010)
Biere, A., Heule, M., van Maaren, H., Walsh, T. (eds.): Handbook of Satisfiability, Frontiers in Artificial Intelligence and Applications, vol. 185. IOS Press, Amsterdam (2009)
Bryant, R.E.: Graph-based algorithms for Boolean function manipulation. IEEE-TC 35(8), 677–691 (1986)
De Vos, A., Rentergem, Y.: Young subgroups for reversible computers. Adv. Math. Commun. 2(2), 183–200 (2008)
Eén, N., Mishchenko, A., Amla, N.: A single-instance incremental SAT formulation of proof- and counterexample-based abstraction. In: FMCAD, pp. 181–188 (2010)
Große, D., Wille, R., Dueck, G.W., Drechsler, R.: Exact multiple-control Toffoli network synthesis with SAT techniques. TCAD 28(5), 703–715 (2009)
Gupta, P., Agrawal, A., Jha, N.K.: An algorithm for synthesis of reversible logic circuits. TCAD 25(11), 2317–2330 (2006)
Järvisalo, M., Biere, A., Heule, M.: Blocked clause elimination. In: Esparza, J., Majumdar, R. (eds.) TACAS 2010. LNCS, vol. 6015, pp. 129–144. Springer, Heidelberg (2010)
Miller, D.M., Maslov, D., Dueck, G.W.: A transformation based algorithm for reversible logic synthesis. In: DAC, pp. 318–323 (2003)
Plaisted, D.A., Greenbaum, S.: A structure-preserving clause form translation. JSC 2(3), 293–394 (1986)
Sinz, C.: Towards an optimal CNF encoding of boolean cardinality constraints. In: CP, pp. 827–831 (2005)
Soeken, M., Chattopadhyay, A.: Fredkin-enabled transformation-based reversible logic synthesis. In: ISMVL, pp. 60–65 (2015)
Soeken, M., Frehse, S., Wille, R., Drechsler, R.: RevKit: a toolkit for reversible circuit design. Multiple-Valued Logic Soft Comput. 18(1), 55–65 (2012)
Soeken, M., Tague, L., Dueck, G.W., Drechsler, R.: Ancilla-free synthesis of large reversible functions using binary decision diagrams. JSC 73, 1–26 (2016)
Soeken, M., Wille, R., Hilken, C., Przigoda, N., Drechsler, R.: Synthesis of reversible circuits with minimal lines for large functions. In: ASP-DAC, pp. 85–92 (2012)
Soeken, M., Wille, R., Keszocze, O., Miller, D.M., Drechsler, R.: Embedding of large Boolean functions for reversible logic. JETC (2015). arXiv:1408.3586
Takahashi, Y., Tani, S., Kunihiro, N.: Quantum addition circuits and unbounded fan-out. Quantum Inf. Comput. 10(9&10), 872–890 (2010)
Touati, H.J., Savoj, H., Lin, B., Brayton, R.K., Sangiovanni-Vincentelli, A.L.: Implicit state enumeration of finite state machines using BDDs. In: ICCAD, pp. 130–133 (1990)
Wegener, I.: The size of reduced OBDDs and optimal read-once branching programs for almost all Boolean functions. IEEE Trans. Comput. 43(11), 1262–1269 (1994)
Wille, R., Große, D., Dueck, G.W., Drechsler, R.: Reversible logic synthesis with output permutation. In: VLSI Design, pp. 189–194 (2009)
Acknowledgments
This research was supported by H2020-ERC-2014-ADG 669354 CyberCare and by the European COST Action IC 1405 ‘Reversible Computation’.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this paper
Cite this paper
Soeken, M., Dueck, G.W., Miller, D.M. (2016). A Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis. In: Devitt, S., Lanese, I. (eds) Reversible Computation. RC 2016. Lecture Notes in Computer Science(), vol 9720. Springer, Cham. https://doi.org/10.1007/978-3-319-40578-0_22
Download citation
DOI: https://doi.org/10.1007/978-3-319-40578-0_22
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-40577-3
Online ISBN: 978-3-319-40578-0
eBook Packages: Computer ScienceComputer Science (R0)