Abstract
The hardware address translation mechanism is an essential part of modern microprocessor memory management. The ever-growing demand for performance and low power of integrated circuits makes this mechanism exceptionally complex, and its verification requires sophisticated test generation tools. This paper presents a solution, based on constraint satisfaction, to generate stimuli for testing address translation.
The address translation process passes through a sequence of steps and can therefore be naturally described as a directed acyclic graph. We developed a framework that we call graph-based constraint satisfaction problems (GCSP). These problems consist of a directed graph, combined with a CSP, where each variable and constraint of the CSP is linked to a particular node or edge of the graph. A solution to the problem is a path in the graph, such that all constraints defined along this path must be satisfied. We base our algorithm for solving GCSPs on conditional CSP. We successfully used this technology to verify the memory management units of several industrial microprocessors.
E. Tsanko and M. Veksler—Work done while this author was at IBM Research.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsNotes
- 1.
IBM, the IBM logo, and ibm.com are trademarks or registered trademarks of International Business Machines Corp., registered in many jurisdictions worldwide. Other product and service names might be trademarks of IBM or other companies. A current list of IBM trademarks is available on the Web at “Copyright and trademark information” at www.ibm.com/legal/copytrade.shtml.
- 2.
The definition for ACSP that we provide here is slightly different, yet equivalent to the definition in [13].
- 3.
For two constraints \(c_1,~c_2\) such that \(AS(c_1)=AS(c_2)\), and a variable v which is a parameter of both constraints, it is sufficient to create one shadow variable.
References
ARM architecture reference manual, ARMv8 for ARMv8-A architecture profile
Adir, A., Almog, E., Fournier, L., Marcus, E., Rimon, M., Vinov, M., Ziv, A.: Genesys-Pro: innovations in test program generation for functional processor verification. IEEE Des. Test Comput. 21(2), 84–93 (2004)
Adir, A., Emek, R., Katz, Y., Koyfman, A.: DeepTrans - a model-based approach to functional verification of address translation mechanisms. In: Fourth International Workshop on Microprocessor Test and Verification, Common Challenges and Solutions (MTV 2003), pp. 3–6 (2003)
Adir, A., Fournier, L., Katz, Y., Koyfman, A.: DeepTrans - extending the model-based approach to functional verification of address translation mechanisms. In: HLDVT, pp. 102–110. IEEE Computer Society (2006)
Adir, A., Golubev, M., Landa, S., Nahir, A., Shurek, G., Sokhin, V., Ziv, A.: Threadmill: a post-silicon exerciser for multi-threaded processors. In: DAC, pp. 860–865. ACM (2011)
Anderson, T., Dahlin, M., Systems, O.: Principles and Practice. Memory Management, vol. 3. Recursive Books (2015)
Blum, A.L., Furst, M.L.: Fast planning through planning graph analysis. Artif. Intell. 90(1–2), 1636–1642 (1997)
Cambazard, H., Bourreau, E.: Conception d’une contrainte globale de chemin. In: JNPC, pp. 107–121 (2004)
Do, M.B., Kambhampati, S.: Planning as constraint satisfaction: solving the planning-graph by compiling it into CSP. Artif. Intell. 132(2), 151–182 (2001)
Dooms, G., Deville, Y., Dupont, P.E.: CP(Graph): introducing a graph computation domain in constraint programming. In: Beek, P. (ed.) CP 2005. LNCS, vol. 3709, pp. 211–225. Springer, Heidelberg (2005)
Fages, J.G.: Exploitation de structures de graphe en programmation par contraintes. Ph.D. thesis, Ecole des Mines de Nantes (2014)
Geller, F., Veksler, M.: Assumption-based pruning in conditional CSP. In: Beek, P. (ed.) CP 2005. LNCS, vol. 3709, pp. 241–255. Springer, Heidelberg (2005)
Hamid, A.: Surveying the verification landscape. http://electronicdesign.com/eda/surveying-verification-landscape
Kamkin, A., Protsenko, A., Tatarnikov, A.: An approach to test program generation based on formal specifications of caching and address translation mechanisms, vol. 27, pp. 125–138 (2015)
Kornykhin, E.V.: Generation of test data for verification of caching mechanisms and address translation in microprocessors. Program. Comput. Softw. 36(1), 28–35 (2010)
Mittal, S., Falkenhainer, B.: Dynamic constraint satisfaction problems. In: AAAI, pp. 25–32. AAAI Press (1990)
Naveh, Y., Rimon, M., Jaeger, I., Katz, Y., Vinov, M., Marcus, E., Shurek, G.: Constraint-based random stimuli generation for hardware verification. In: IAAI, pp. 1720–1727. AAAI Press (2006)
Le Pape, C., Régin, J.-C., Shaw, P.: Robust and parallel solving of a network design problem. In: Hentenryck, P. (ed.) CP 2002. LNCS, vol. 2470, pp. 633–648. Springer, Heidelberg (2002)
Romanescu, B.F., Lebeck, A.R., Sorin, D.J.: Specifying and dynamically verifying address translation-aware memory consistency. In: ASPLOS, pp. 323–334. ACM (2010)
Sabin, M., Freuder, E.C., Wallace, R.J.: Greater efficiency for conditional constraint satisfaction. In: Rossi, F. (ed.) CP 2003. LNCS, vol. 2833, pp. 649–663. Springer, Heidelberg (2003)
Acknowledgments
Many people helped in discussions and in implementation of models for different architectures. In particular, we would like to warmly thank Ahmed Issa, Adi Dagan, Asaf Slilat, Elad Venezian, Oz Hershkovitz, Michal Rimon, Karen Holtz, and Alexandra Skolzub for using our technology and providing important insights.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
1 Electronic supplementary material
Below is the link to the electronic supplementary material.
Rights and permissions
Copyright information
© 2016 Springer International Publishing Switzerland
About this paper
Cite this paper
Aharoni, M., Ben-Haim, Y., Doron, S., Koyfman, A., Tsanko, E., Veksler, M. (2016). Using Graph-Based CSP to Solve the Address Translation Problem. In: Rueher, M. (eds) Principles and Practice of Constraint Programming. CP 2016. Lecture Notes in Computer Science(), vol 9892. Springer, Cham. https://doi.org/10.1007/978-3-319-44953-1_53
Download citation
DOI: https://doi.org/10.1007/978-3-319-44953-1_53
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-44952-4
Online ISBN: 978-3-319-44953-1
eBook Packages: Computer ScienceComputer Science (R0)