Abstract
To protect integrated circuits against IP piracy, Physically Unclonable Functions (PUFs) are deployed. PUFs provide a specific signature for each integrated circuit. However, environmental variations, (e.g., temperature change), power supply noise and more influential IC aging affect the functionally of PUFs. Thereby, it is important to evaluate aging effects as early as possible, preferentially at design time. In this paper we investigate the effect of aging on the stability of two delay PUFs: arbiter-PUFs and loop-PUFs and analyze the architectural impact of these PUFS on reliability decrease due to aging.
We observe that the reliability of the arbiter-PUF gets worse over time, whereas the reliability of the loop-PUF remains constant. We interpret this phenomenon by the asymmetric aging of the arbiter, because one half is active (hence aging fast) while the other is not (hence aging slow). Besides, we notice that the aging of the delay chain in the arbiter-PUF and in the loop-PUF has no impact on their reliability, since these PUFs operate differentially.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Gassend, B., Clarke, D., van Dijk, M., Devadas, S.: Controlled physical random functions. In: Computer Security Applications Conference, pp. 149–160 (2002)
Suh, G.E., Devadas, S.: Physical unclonable functions for device authentication and secret key generation. In: Design Automation Conference (DAC), pp. 9–14 (2007)
Guajardo, J., Kumar, S.S., Schrijen, G.-J., Tuyls, P.: FPGA intrinsic PUFs and their use for IP protection. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 63–80. Springer, Heidelberg (2007). doi:10.1007/978-3-540-74735-2_5
Rahman, M.T., Forte, D., Fahrny, J., Tehranipoor, M.: ARO-PUF: An aging-resistant ring oscillator PUF design. In: Design, Automation Test in Europe Conference (DATE), pp. 1–6 (2014)
Cherif, Z., Danger, J., Guilley, S., Bossuet, L.: An easy-to-design PUF based on a single oscillator: the loop PUF. In: Digital System Design (DSD), pp. 156–162 (2012)
Pelgrom, M.J., Duinmaijer, A.C., Welbers, A.P.: Matching properties of MOS transistors. IEEE J. Solid State Circ. 24(5), 1433–1439 (1989)
Holcomb, D.E., Burleson, W.P., Fu, K.: Power-up SRAM state as an identifying fingerprint and source of true random numbers. IEEE Trans. Comput. 58(9), 1198–1210 (2009)
Morozov, S., Maiti, A., Schaumont, P.: An analysis of delay based puf implementations on FPGA. In: Sirisuk, P., Morgan, F., El-Ghazawi, T., Amano, H. (eds.) ARC 2010. LNCS, vol. 5992, pp. 382–387. Springer, Heidelberg (2010). doi:10.1007/978-3-642-12133-3_37
Kufluoglu, H., Alam, M.A.: A generalized reaction-diffusion model with explicit H-H2 dynamics for Negative-Bias Temperature-Instability (NBTI) degradation. IEEE Trans. Electron Devices 54(5), 1101–1107 (2007)
Lu, Y., Shang, L., Zhou, H., Zhu, H., Yang, F., Zeng, X.: Statistical reliability analysis under process variation and aging effects. In: Design Automation Conference (DAC), pp. 514–519, July 2009
Chakravarthi, S., Krishnan, A., Reddy, V., Machala, C.F., Krishnan, S.: A comprehensive framework for predictive modeling of negative bias temperature instability. In: Reliability Physics Symposium, pp. 273–282 (2004)
Saha, D., Varghese, D., Mahapatra, S.: Role of anode hole injection and valence band hole tunneling on interface trap generation during hot carrier injection stress. IEEE Electron Device Lett. 27(7), 585–587 (2006)
Rodriguez, R., Stathis, J., Linder, B.: Modeling and experimental verification of the effect of gate oxide breakdown on CMOS inverters. In: IEEE Int’l Reliability Physics Symposium, pp. 11–16 (2003)
Sinanoglu, O., Karimi, N., Rajendran, J., Karri, R., Jin, Y., Huang, K., Makris, Y.: Reconciling the IC test and security dichotomy. In: European Test Symposium (ETS), pp. 1–6 (2013)
Khan, S., Haron, N.Z., Hamdioui, S., Catthoor, F.: NBTI monitoring and design for reliability in nanoscale circuits. In: Int’l Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 68–76 (2011)
Yuan, J.-S., Yeh, W.-K., Chen, S., Hsu, C.-W.: NBTI reliability on high-k metal-gate SiGe transistor and circuit performances. Microelectron. Reliab. 51(5), 914–918 (2011)
Yu, M., Devadas, S.: Secure and robust error correction for physical unclonable functions. Des. Test of Comput. 27(1), 48–65 (2010)
Kirkpatrick, M.S., Bertino, E.: Software techniques to combat drift in PUF-based authentication systems. In: Workshop on Secure Component and System Identification (SECSI), p. 9 (2010)
Guajardo, J., Kumar, S.S., Schrijen, G.-J., Tuyls, P.: FPGA intrinsic PUFs and their use for IP protection. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 63–80. Springer, Heidelberg (2007). doi:10.1007/978-3-540-74735-2_5
Maes, R., van der Leest, V.: Countering the effects of silicon aging on SRAM PUFs. In: Hardware-Oriented Security and Trust (HOST), pp. 148–153 (2014)
Maiti, A., Schaumont, P.: The impact of aging on a physical unclonable function. IEEE Trans. Very Large Scale Integr. Syst. 22(9), 1854–1864 (2014)
Synopsys. HSPICE User Guide: Basic Simulation and Analysis (2016)
Kim, K.K.: On-chip delay degradation measurement for aging compensation. Indian J. Sci. Technol. 8(8), 777–782 (2015)
Nunes, C., Butzen, P.F., Reis, A.I., Ribas, R.P.: BTI, HCI and TDDB aging impact in flip-flops. Microelectron. Reliab. 53(9–11), 1355–1359 (2013)
Mizan, E.: Efficient fault tolerance for pipelined structures and its application to superscalar and dataflow machines. Ph.D. thesis, Electrical and Computer Engineering Department, University of Texas At Austin (2008)
Alam, M.A., Kufluoglu, H., Varghese, D., Mahapatra, S.: A comprehensive model for PMOS NBTI degradation: Recent progress. Microelectron. Reliab. 47(6), 853–862 (2007)
Mahapatra, S., Saha, D., Varghese, D., Kumar, P.: On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress. IEEE Trans. Electron Devices 53(7), 1583–1592 (2006)
Schroder, D.K.: Negative bias temperature instability: What do we understand? Microelectron. Reliab. 47(6), 841–852 (2007)
Cha, S., Chen, C.-C., Liu, T., Milor, L.S.: Extraction of threshold voltage degradation modeling due to negative bias temperature instability in circuits with I/O measurements. In: VLSI Test Symposium (VTS), pp. 1–6 (2014)
Sutaria, K.B., Velamala, J.B., Ramkumar, A., Cao, Y.: Compact modeling of BTI for circuit reliability analysis. In: Reis, R., Cao, Y., Wirth, G. (eds.) Circuit Design for Reliability, pp. 93–119. Springer, Heidelberg (2015). doi:10.1007/978-1-4614-4078-9_6
Wang, W., Yang, S., Bhardwaj, S., Vrudhula, S., Liu, F., Cao, Y.: The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis. IEEE Trans. Very Large Scale Integr. Syst. 18(2), 173–183 (2010)
Ye, Y., Liu, F., Chen, M., Nassif, S., Cao, Y.: Statistical modeling and simulation of threshold variation under random dopant fluctuations and line-edge roughness. IEEE Trans. VLSI Syst. 19(6), 987–996 (2011)
Nangate 45nm Open Cell Library. http://www.nangate.com. Accessed 1 May, 2016
Rioul, O., Solé, P., Guilley, S., Danger, J.-L.: On the Entropy of Physically Unclonable Functions. In: IEEE Int’l Symposium on Information Theory (ISIT), Barcelona, Spain, July 2016
Hedayat, A.S., Wallis, W.D.: Hadamard matrices, their applications. Ann. Statist. 6(6), 1184–1238 (1978). http://dx.doi.org/10.1214/aos/1176344370
JEDEC. JEP122G : Failure mechanisms and models for semiconductor devices. http://www.jedec.org/standards-documents/docs/jep-122e. October 2011
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer International Publishing AG
About this paper
Cite this paper
Karimi, N., Danger, JL., Lozac’h, F., Guilley, S. (2016). Predictive Aging of Reliability of Two Delay PUFs. In: Carlet, C., Hasan, M., Saraswat, V. (eds) Security, Privacy, and Applied Cryptography Engineering. SPACE 2016. Lecture Notes in Computer Science(), vol 10076. Springer, Cham. https://doi.org/10.1007/978-3-319-49445-6_12
Download citation
DOI: https://doi.org/10.1007/978-3-319-49445-6_12
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-49444-9
Online ISBN: 978-3-319-49445-6
eBook Packages: Computer ScienceComputer Science (R0)