Abstract
The demand from Exascale computing has made the design of high-radix switch chips an attractive and challenging research field in EHPC (Exascale High-Performance Computing). Recent development of silicon photonic and 3D integration technologies has inspired new methods of designing high-radix switch chips. In this paper, we propose Graphein—a novel optical high-radix switch architecture, which significantly reduces the radix of switch network by distributing a high-radix switch network into multiple layers via 3D integration, and which improves switch bandwidth while lowering switch chips power consumption by using silicon photonic technology. Our theoretical analysis shows that Graphein architecture can achieve 100% throughput. Our simulation shows that the average latencies under both random and hotspot patterns are less than 10 cycles, and the throughput under random pattern is almost 100%. Compared to hi-rise architecture, Graphein ensures the packets from different source ports receive fairer service, thereby yielding more concentrated latency distribution. The Graphein architecture also provides strong performance isolation under random traffic pattern. In addition, the power consumption of the Graphein chip is about 19.2 W, which totally satisfies the power constraint on a high-radix switch chip.
J. Jian—This work was partially supported by 863 Program of China (2015AA015302), NSFC (61572509).
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Jian, J., Lai, M., Xiao, L., Xu, W. (2016). Graphein: A Novel Optical High-Radix Switch Architecture for 3D Integration. In: Carretero, J., Garcia-Blas, J., Ko, R., Mueller, P., Nakano, K. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2016. Lecture Notes in Computer Science(), vol 10048. Springer, Cham. https://doi.org/10.1007/978-3-319-49583-5_12
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