Abstract
The main contribution of this paper is to present a new hardware architecture for accelerating LZW compression using an FPGA. In the proposed architecture, we efficiently use dual-port block RAMs embedded in the FPGA to implement a hash table that is used as a dictionary. Using independent two ports of the block RAM, reading and writing operations for the hash table are performed simultaneously. Additionally, we can read eight values in the hash table in one clock cycle by partitioning the hash table into eight tables. Since the proposed hardware implementation of LZW compression is compactly designed, we have succeeded in implementing 24 identical circuits in an FPGA, where the clock frequency of FPGA is 163.35 MHz. Our implementation of 24 proposed circuits attains a speed up factor of 23.51 times faster than a sequential LZW compression on a single CPU.
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Zhou, X., Ito, Y., Nakano, K. (2016). An Efficient Implementation of LZW Compression in the FPGA. In: Carretero, J., Garcia-Blas, J., Ko, R., Mueller, P., Nakano, K. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2016. Lecture Notes in Computer Science(), vol 10048. Springer, Cham. https://doi.org/10.1007/978-3-319-49583-5_39
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DOI: https://doi.org/10.1007/978-3-319-49583-5_39
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