Abstract
Emerging applications such as the Internet of Things require security solutions that are small, low power and low cost, yet provide solid protection against a wide range of sophisticated attacks. Lightweight cryptographic schemes such as the Speck cipher that was recently proposed by the NSA aim to solve some of these challenges. However, before using Speck in any practical application, sound protection against side-channel attacks must be in place. In this work, we propose a bit-serialized implementation of Speck, to achieve minimal area footprint. We further propose a Speck core that is provably secure against first-order side-channel attacks using a Threshold Implementation technique which depends on secure multi-party computation. The resulting design is a tiny crypto core that provides AES-like security in under 40 slices on a low-cost Xilinx Spartan 3 FPGA. The first-order side-channel resistant version of the same core needs less than 100 slices. Further, we validate the security of the protected core by state-of-the-art side-channel leakage detection tests.
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This work is supported by the National Science Foundation under grants CNS-1314770 and CNS-1261399.
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Chen, C., İnci, M.S., Taha, M., Eisenbarth, T. (2017). SpecTre: A Tiny Side-Channel Resistant Speck Core for FPGAs. In: Lemke-Rust, K., Tunstall, M. (eds) Smart Card Research and Advanced Applications. CARDIS 2016. Lecture Notes in Computer Science(), vol 10146. Springer, Cham. https://doi.org/10.1007/978-3-319-54669-8_5
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DOI: https://doi.org/10.1007/978-3-319-54669-8_5
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