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Low Dose-Rate, High Total Dose Set-Up for Rad-Hard CMOS I/O Circuits Testing

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Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 429))

Abstract

In this paper, the planning of low dose-rate, high total dose testing campaign for I/O circuits is reported. In particular, the paper describes all development steps, starting from the rad-hard I/O circuits design and the implementation of the test-chip, which is meant to allow comparative testing between rad-hard and standard devices. The designed experimental setup permits in situ measurements, therefore the circuits behavior can be remotely monitored for very long periods. This feature enables low dose-rate testing up to very high dose.

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References

  1. Maureret, R.H., et al.: Harsh environments: space radiation environment, effects and mitigation. J. Hopkins APL Tech. Dig. 28(1), 17–29 (2008)

    Google Scholar 

  2. Schwank, J.R., et al.: Radiation effect in MOS oxides. IEEE Trans. Nucl. Sci. 55(4), 1833–1853 (2008)

    Article  Google Scholar 

  3. Oldham, T.R.: Total ionizing dose effects in MOS oxides and devices. IEEE Trans. Nucl. Sci. 50(3), 483–499 (2003)

    Article  Google Scholar 

  4. Barnaby, H.: Total-ionizing-dose effects in modern CMOS technologies. IEEE Trans. Nucl. Sci. 53(6), 3103–3121 (2006)

    Article  Google Scholar 

  5. Yusoff, Y., et al.: Design and characterization of input and output (I/O) pads. IEEE Int. Conf. Semicond. Electron. (2004)

    Google Scholar 

  6. Dabral, S., Maloney, T.: Basic ESD and I/O Design. Wiley (1998)

    Google Scholar 

  7. Witczak, S.C., et al.: Dose-rate sensitivity of modern nMOSFETs. IEEE Trans. Nucl. Sci. 52(6) (2005)

    Google Scholar 

  8. Lisiansky, M., et al.: Radiation tolerance of NROM embedded products. IEEE Trans. Nucl. Sci. 57(4) (2010)

    Google Scholar 

  9. Libertino, S., et al.: Ionizing radiation effects on non volatile read only memory cells. IEEE Trans. Nucl. Sci. 59(6) (2012)

    Google Scholar 

  10. Johnston, A.H., et al.: Low dose rate effects in shallow trench isolation regions. IEEE Trans. Nucl. Sci. 57(6) (2010)

    Google Scholar 

  11. Amerasekera, A., Duvvury, C.: ESD in Silicon Integrated Circuits, 2nd ed. Wiley (2002)

    Google Scholar 

  12. Cappello, S.G., et al.: Gamma-ray irradiation test of CMOS sensors used in imaging techniques. Nucl. Technol. Radiat. Protect. 29, Suppl., pp. S14–S19 (2014). doi:10.2298/NTRP140SS14C

  13. European Space Agency. Total dose steady-state irradiation test method (2010). https://escies.org/webdocument/showArticle?id=229

  14. Lawrence, T.C., et al.: Radiation hardened by design digital I/O for high SEE and TID immunity. IEEE Trans. Nucl. Sci. 56(6) (2009)

    Google Scholar 

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Acknowledgements

This work was supported by the European Union’s H2020 research and innovation programme under grant agreement No 640,073.

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Correspondence to Calogero Pace .

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© 2018 Springer International Publishing AG

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Pace, C., Fragomeni, L., Parlato, A., Solano, A., Marchese, N., Fiore, D. (2018). Low Dose-Rate, High Total Dose Set-Up for Rad-Hard CMOS I/O Circuits Testing. In: De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2016. Lecture Notes in Electrical Engineering, vol 429. Springer, Cham. https://doi.org/10.1007/978-3-319-55071-8_4

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  • DOI: https://doi.org/10.1007/978-3-319-55071-8_4

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-55070-1

  • Online ISBN: 978-3-319-55071-8

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