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International Symposium on Applied Reconfigurable Computing

ARC 2017: Applied Reconfigurable Computing pp 289–296Cite as

FPGA Implementation of a Short Read Mapping Accelerator

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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 10216))

Abstract

Recently, due to drastically reducing costs of sequencing a human DNA molecule, the demands for next generation DNA sequencing (NGS) has increased significantly. DNA sequencers deliver millions of small fragments (short reads) from random positions of a very large DNA stream. To align these short-reads such that the original DNA sequence is determined, various software tools called short read mappers, such as Burrows BWA, are available. Analyzing the massive quantities of sequenced data produced using these software tools, requires a very long run-time on general-purpose computing systems due to a great computational power it needs. This work proposes some methods to accelerate short read alignment being prototyped on an FPGA. We use a seed and compare architecture based on FM-index method. Also pre-calculated data are used for more performance improvement. A multi-core accelerator based on the proposed methods is implemented on a Xilinx Virtex-6. Our design performs alignment of short reads with length of 75 and up to two mismatches. The proposed parallel architecture performs the short-read mapping up to 41 and 19 times faster than parallel programmed BWA run on eight-core AMD FX9590 and 6-cores Intel Extreme Core i7-5820 k CPUs using 8 and 12 threads.

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Author information

Authors and Affiliations

  1. Faculty of Engineering, Electrical Engineering Department, Ferdowsi University of Mashhad, Mashhad, Iran

    Mostafa Morshedi & Hamid Noori

Authors
  1. Mostafa Morshedi
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  2. Hamid Noori
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Corresponding author

Correspondence to Hamid Noori .

Editor information

Editors and Affiliations

  1. Delft University of Technology, Delft, The Netherlands

    Stephan Wong

  2. Federal University of Rio Grande do Sul, Porto Alegre, Brazil

    Antonio Carlos Beck

  3. Delft University of Technology, Delft, The Netherlands

    Koen Bertels

  4. Federal University of Rio Grande do Sul, Porto Alegre, Brazil

    Luigi Carro

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Morshedi, M., Noori, H. (2017). FPGA Implementation of a Short Read Mapping Accelerator. In: Wong, S., Beck, A., Bertels, K., Carro, L. (eds) Applied Reconfigurable Computing. ARC 2017. Lecture Notes in Computer Science(), vol 10216. Springer, Cham. https://doi.org/10.1007/978-3-319-56258-2_25

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  • DOI: https://doi.org/10.1007/978-3-319-56258-2_25

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-56257-5

  • Online ISBN: 978-3-319-56258-2

  • eBook Packages: Computer ScienceComputer Science (R0)

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