A Dynamic Area-Efficient Technique to Enhance ROPUFs Security Against Modeling Attacks

Abstract

Physical Unclonable Function PUFs are probabilistic functions that are widely used for the security of silicon technology chips including ASIC/FPGA. Despite the prevalence of numerous techniques for fabrication of Silicon PUFs (SPUFs), to the best of our knowledge, a well-established dynamic technique that can provide updated secret keys to improve ROPUF security against modeling attacks does not exist. In this book chapter, an area-efficient technique that exploits an appropriate reconfiguration mechanism and utilizes dedicated FPGA resources to build a dynamic multi-stage ROPUF (d-ROPUF) structures is proposed. To determine the correlation between each structure and its performance, the normality of the generated RO frequencies is studied. Experimental results show that a structure with fewer stages has higher performance in terms of variability and diverseness. Statistical characteristics of the response bits are studied at normal and varying temperature and voltage variations in order to validate the performance of the proposed technique in terms of uniqueness, uniformity, bit-aliasing, and reliability. Our results show that the d-ROPUF exhibits better uniqueness, uniformity, bit-aliasing, and reliability at varying operating conditions when compared with other techniques.