Skip to main content

Energy Optimization of Unrolled Block Ciphers Using Combinational Checkpointing

  • Conference paper
  • First Online:

Part of the book series: Lecture Notes in Computer Science ((LNSC,volume 10155))

Abstract

Energy consumption of block ciphers is critical in resource constrained devices. Unrolling has been explored in literature as a technique to increase efficiency by eliminating energy spent in loop control elements such as registers and multiplexers. However these savings are minimal and are offset by the increase in glitching power that comes with unrolling. We propose an efficient latch-based glitch filter for unrolled designs that reduces energy per encryption by an order of magnitude over a straightforward implementation, and by 28–32% over the best existing glitch filtering schemes. We explore the optimal number of glitch filters that should be used in order to minimize total energy, and provide estimates of the area cost. Partially unrolled designs also benefit from using our scheme with energies competitive to fully serialized implementations. We demonstrate our approach on the SIMON-128 and AES-256 block ciphers.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

References

  1. NCSU Free PDK 45. http://www.eda.ncsu.edu/wiki/FreePDK45:Contents

  2. Athas, W.C., Svensson, L.J., Koller, J.G., Tzartzanis, N., Chou, E.Y.-C.: Low-power digital systems based on adiabatic-switching principles. IEEE Trans. Very Large Scale Integr. VLSI Syst. 2(4), 398–407 (1994)

    Article  Google Scholar 

  3. Banik, S., Bogdanov, A., Regazzoni, F.: Exploring energy efficiency of lightweight block ciphers. In: Dunkelman, O., Keliher, L. (eds.) SAC 2015. LNCS, vol. 9566, pp. 178–194. Springer, Cham (2016). doi:10.1007/978-3-319-31301-6_10

    Chapter  Google Scholar 

  4. Banik, S., Bogdanov, A., Regazzoni, F., Isobe, T., Hiwatari, H., Akishita, T.: Round gating for low energy block ciphers. In: IEEE International Symposium on Hardware Oriented Security and Trust (HOST), pp. 55–60, May 2016

    Google Scholar 

  5. Batina, L., Das, A., Ege, B., Kavun, E.B., Mentens, N., Paar, C., Verbauwhede, I., Yalçın, T.: Dietary recommendations for lightweight block ciphers: power, energy and area analysis of recently developed architectures. In: Hutter, M., Schmidt, J.-M. (eds.) RFIDSec 2013. LNCS, vol. 8262, pp. 103–112. Springer, Heidelberg (2013). doi:10.1007/978-3-642-41332-2_7

    Chapter  Google Scholar 

  6. Beaulieu, R., Shors, D., Smith, J., Treatman-Clark, S., Weeks, B., Wingers, L.: The simon and speck families of lightweight block ciphers. Cryptology ePrint Archive, Report 2013/404 (2013). http://eprint.iacr.org/2013/404

  7. Benini, L., Micheli, G.D., Macii, A., Macii, E., Poncino, M., Scarsi, R.: Glitch power minimization by selective gate freezing. IEEE Trans. Very Large Scale Integr. VLSI Syst. 8(3), 287–298 (2000)

    Article  Google Scholar 

  8. Boemo, E., Oliver, J.P., Caffarena, G.: Tracking the pipelining-power rule along the FPGA technical literature. In: Proceedings of the 10th FPGAworld Conference, FPGAworld 2013, New York, pp. 9:1–9:5. ACM (2013)

    Google Scholar 

  9. Hanson, S., Zhai, B., Bernstein, K., Blaauw, D., Bryant, A., Chang, L., Das, K.K., Haensch, W., Nowak, E.J., Sylvester, D.M.: Ultralow-voltage, minimum-energy CMOS. IBM J. Res. Dev. 50(4.5), 469–490 (2006)

    Article  Google Scholar 

  10. Hsing, H.: Tiny AES project. opencores.org/project,tiny_aes

  11. Huda, S., Anderson, J.: Towards PVT-tolerant glitch-free operation in FPGAs. In: Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2016, New York, pp. 90–99. ACM (2016)

    Google Scholar 

  12. Karthik, H.S., Naik, B.M.K.: Glitch elimination and optimization of dynamic power dissipation in combinational circuits. In: 2014 International Conference on Advances in Electronics, Computers and Communications (ICAECC), pp. 1–6, October 2014

    Google Scholar 

  13. Kerckhof, S., Durvaux, F., Hocquet, C., Bol, D., Standaert, F.-X.: Towards green cryptography: a comparison of lightweight ciphers from the energy viewpoint. In: Prouff, E., Schaumont, P. (eds.) CHES 2012. LNCS, vol. 7428, pp. 390–407. Springer, Heidelberg (2012). doi:10.1007/978-3-642-33027-8_23

    Chapter  Google Scholar 

  14. Lamoureux, J., Lemieux, G.G.F., Wilton, S.J.E.: GlitchLess: dynamic power minimization in FPGAs through edge alignment and glitch filtering. IEEE Trans. Very Large Scale Integr. VLSI Syst. 16(11), 1521–1534 (2008)

    Article  Google Scholar 

  15. Monteiro, J., Devadas, S., Ghosh, A.: Retiming sequential circuits for low power. In: IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1993. Digest of Technical Papers, pp. 398–402, November 1993

    Google Scholar 

  16. Musoll, E., Cortadella, J.: Low-power array multipliers with transition-retaining barriers. In: Power and Timing Modeling, Optimization and Simulation (PATMOS), pp. 227–238, October 1995

    Google Scholar 

  17. Pub, N.F.: 197: Advanced encryption standard (AES). Federal Information Processing Standards Publication 197, 441–0311 (2001)

    Google Scholar 

  18. Tiri, K., Verbauwhede, I.: A digital design flow for secure integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7), 1197–1208 (2006)

    Article  Google Scholar 

  19. Wilton, S.J.E., Ang, S.-S., Luk, W.: The impact of pipelining on energy per operation in field-programmable gate arrays. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, vol. 3203, pp. 719–728. Springer, Heidelberg (2004). doi:10.1007/978-3-540-30117-2_73

    Chapter  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Siva Nishok Dhanuskodi .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2017 Springer International Publishing AG

About this paper

Cite this paper

Dhanuskodi, S.N., Holcomb, D. (2017). Energy Optimization of Unrolled Block Ciphers Using Combinational Checkpointing. In: Hancke, G., Markantonakis, K. (eds) Radio Frequency Identification and IoT Security. RFIDSec 2016. Lecture Notes in Computer Science(), vol 10155. Springer, Cham. https://doi.org/10.1007/978-3-319-62024-4_4

Download citation

  • DOI: https://doi.org/10.1007/978-3-319-62024-4_4

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-62023-7

  • Online ISBN: 978-3-319-62024-4

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics