Abstract
In this paper, we investigate the case for model checking in the WCET analysis of pipelined processors with dynamic branch and target prediction. We consider a microarchitecture inspired by the e200z4 Power 32-bit architecture, with an instruction cache, a dynamic branch prediction mechanism, a branch target buffer (BTB) and an instruction prefetch buffer. The conjoint operation of all these components produce a very complex behaviour that is difficult to analyse with tight and sound static analysis techniques. We show that model checking techniques can actually be used to compute WCET bounds for this kind of architectures.
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Notes
- 1.
Metzner use dynamic analysis to designate techniques that analyze concrete paths in the system, as opposed to static analysis that consider abstract paths.
- 2.
The main difference is that the e200z4 is actually a two issues statically scheduled superscalar processor, whereas we consider a single issue processor.
- 3.
A bubble, or pipeline stall, is a delay cycle. When a bubble enters a stage, this stage has no activity during the current cycle.
- 4.
The Advanced High-performance Bus is part of the open standard ARM-AMBA on-chip interconnect specification.
- 5.
In the case where the instruction in the decode stage requires a result produced by an instruction ahead in the pipeline, bubbles are inserted until the availability of the result. This is a data hazard. Bypasses are used between stages to propagate results and limits these bubbles.
- 6.
Available at https://github.com/TrampolineRTOS/BEST.
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Mangean, A., Béchennec, JL., Briday, M., Faucou, S. (2017). WCET Analysis by Model Checking for a Processor with Dynamic Branch Prediction. In: Barkaoui, K., Boucheneb, H., Mili, A., Tahar, S. (eds) Verification and Evaluation of Computer and Communication Systems. VECoS 2017. Lecture Notes in Computer Science(), vol 10466. Springer, Cham. https://doi.org/10.1007/978-3-319-66176-6_5
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