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A Formal Model of Parallel Execution on Multicore Architectures with Multilevel Caches

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Book cover Formal Aspects of Component Software (FACS 2017)

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Abstract

The performance of software running on parallel or distributed architectures can be severely affected by the location of data. On shared memory multicore architectures, data movement between caches and main memory is driven by tasks executing in parallel on different cores and by a protocol to ensure cache coherence, such as MSI. This paper integrates MSI in a formal model to capture such data movement from an application perspective. We develop an executable model which integrates cache coherent data movement between different cache levels and main memory, for software described by task-level data access patterns. The proposed model is generic in the number of cache levels and cores, and abstracts from the concrete communication medium. We show that the model guarantees expected correctness properties for the MSI protocol, in particular data consistency. This paper further presents a proof of concept implementation of the proposed model in rewriting logic, which allows different choices for a program’s underlying hardware architecture to be specified and compared.

Supported by the EU project FP7-612985 UpScale: From Inherent Concurrency to Massive Parallelism through Type-based Optimizations  (www.upscale-project.eu) and the SIRIUS Centre for Scalable Data Access  (www.sirius-labs.no).

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Notes

  1. 1.

    The proof of concept implementation in Maude and the complete example scenarios can be downloaded from http://folk.uio.no/shijib/multilevel.zip.

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Authors and Affiliations

  1. Department of Informatics, University of Oslo, Oslo, Norway

    Shiji Bijo, Einar Broch Johnsen, Ka I Pun & Silvia Lizeth Tapia Tarifa

Authors
  1. Shiji Bijo
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  2. Einar Broch Johnsen
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  3. Ka I Pun
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  4. Silvia Lizeth Tapia Tarifa
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Correspondence to Ka I Pun .

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Editors and Affiliations

  1. University of Minho, Braga, Portugal

    José Proença

  2. Swinburne University of Technology, Hawthorn, Victoria, Australia

    Markus Lumpe

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Bijo, S., Johnsen, E.B., Pun, K.I., Tapia Tarifa, S.L. (2017). A Formal Model of Parallel Execution on Multicore Architectures with Multilevel Caches. In: Proença, J., Lumpe, M. (eds) Formal Aspects of Component Software. FACS 2017. Lecture Notes in Computer Science(), vol 10487. Springer, Cham. https://doi.org/10.1007/978-3-319-68034-7_4

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