Abstract
Designing efficient branch predictors has always been one of the top priority research tasks in computer architecture. In an embedded processor with support for multi-threaded execution, with multiple different applications executing in different threads, and managed by a single predictor, significant inter-application interference due to sharing of predictor data structures has been acknowledged to be a serious concern. In this paper, we show an attack methodology which exploits these shared structures for performance attacks on a benign application. In particular, we propose a methodology for creating a variant of a benign application, which when dispatched in a concurrently executing thread, can definitively slow down the performance of the benign one. We report the effect of such attacks with experiments on the Siemens software benchmarks.
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Acknowledgement
This work was partially funded by a research grant from Defence Research and Development Organization, Government of India awarded to Indian Statistical Institute. The authors would like to thank Prof. Sandeep Shukla and Prof. Mainak Chaudhuri of IIT Kanpur for their suggestions on this work.
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Das, M., Banerjee, A., Singh, N.K., Sardar, B. (2017). Performance Attacks on Branch Predictors in Embedded Processors with SMT Support. In: Shyamasundar, R., Singh, V., Vaidya, J. (eds) Information Systems Security. ICISS 2017. Lecture Notes in Computer Science(), vol 10717. Springer, Cham. https://doi.org/10.1007/978-3-319-72598-7_19
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DOI: https://doi.org/10.1007/978-3-319-72598-7_19
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