A 100 MHz SRAM Design in 180 nm Process

Abstract

With the development of integrated circuit, SoC systems are more and more used in products. Memory is an important part of SoC, SRAM design is a key research area. In this paper, based on ASIC design methodology, 2 K-bits SRAM is designed. A 6T-SRAM memory cell is designed and simulated with circuit level to improve reliability. The memory cell is used to construct the storage array, which are the word line 32 bits and the bit line 8 bits. Then, the SRAM peripheral circuit is designed and simulated by using SMIC 0.18 μm process, including the data input/output buffer circuit, clock circuit, address decoding circuit, data read/write circuit and sense amplifier. The structure, function and performance of latch type sense amplifier are analyzed emphatically. The simulation results demonstrate that the function of SRAM is verified correctly. The clock frequency of the SRAM can reach 100 MHz.