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Cellular Nonlinear Networks with Memristor Synapses

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Abstract

Cellular Nonlinear/Nanoscale Networks (CNNs) that can provide parallel processing in massive scale is known suitable to neuromorphic applications such as vision systems. In CNN, synaptic weights can be calculated by digital or analog multiplication. Though the conventional CMOS digital circuits can be used in calculating this multiplication for CNN applications, they occupy very large area and need large power consumption, especially when many multiplications should be calculated in parallel in massive scale. On the other hand, analog circuits seem very attractive in calculating multiplication of CNN applications. Here input signal current is multiplied by memristance that can be programmed. In this chapter, we introduce some analog circuits for CNN applications that use memristance in calculating multiplication. In addition, we discuss memristor models and some practical problems in CNN circuits that should be resolved in real implementation of CNN circuits.

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Notes

  1. 1.

    In the following memsitive systems are referred to as memristor systems, whereas the term ideal memristor is used for systems described by (1).

  2. 2.

    For the sake of brevity the explicit time dependency is dropped where it is not strictly necessary.

  3. 3.

    Note that by defining a time evolution rule for the threshold voltages, it was recently demonstrated [23] that an adaptable threshold voltage-based version of the memristor model from [6] may explain the Suppression Principle [24] of the Spike-Timing-Dependent-Plasticity (STDP) Rule [6], which may occur in the case of triplet spikes.

  4. 4.

    Throughout the paper, unless stated otherwise and without loss of generality, we assume that the doped layer is spatially located to the left of the un-doped layer along the horizontal extension of the nano-film [20], and in this case we assign a value of \(+1\) to the memristor polarity coefficient \(\eta \) (see Eq. (6)).

  5. 5.

    Nonlinear memristors models, including the generalized BCM model, will be considered in the forthcoming publications.

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Acknowledgements

This work was partially supported by the CRT Foundation, under the project no. 2012.1121 and by the Ministry of Foreign Affairs “Con il contributo del Ministero degli Affari Esteri, Direzione Generale per la Promozione del Sistema Paese”.

The CAD tools were supported by the IC Design Education Center (IDEC), Korea. This work was financially supported by NRF-2013K1A3A1A25038533through the National Research Foundation of Korea(NRF) funded by the Ministry of Science, ICT & Future Planning.

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Authors and Affiliations

  1. Politecnico di Torino, Corso Duca degli Abruzzi 24, 10129, Torino, Italy

    Fernando Corinto

  2. Technische Universität Dresden, Mommsenstraße 12, 01062, Dresden, Germany

    Alon Ascoli

  3. School of Electrical Engineering, Kookmin University Seoul, Seoul, Korea

    Young-Su Kim & Kyeong-Sik Min

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  1. Fernando Corinto
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  2. Alon Ascoli
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  3. Young-Su Kim
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  4. Kyeong-Sik Min
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Correspondence to Alon Ascoli .

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Editors and Affiliations

  1. Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, USA

    Leon Chua

  2. Democritus University of Thrace, Xanthi, Greece

    Georgios Ch. Sirakoulis

  3. Department of Computer Science and Creative Technologies, University of the West of England, Bristol, UK

    Andrew Adamatzky

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Corinto, F., Ascoli, A., Kim, YS., Min, KS. (2019). Cellular Nonlinear Networks with Memristor Synapses. In: Chua, L., Sirakoulis, G., Adamatzky, A. (eds) Handbook of Memristor Networks. Springer, Cham. https://doi.org/10.1007/978-3-319-76375-0_23

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