Abstract
Developing a new microchip for an embedded application these days means that the engineer has to take many different design options into account. Evaluating the different processor cores regarding their runtime for a certain algorithm requires simulation tools which make emulation feasible. They come in two flavors: Cycle and instruction accurate simulation. The first one offers a high accuracy regarding the estimated time but is very slow. The second one offers a high simulation speed but only provides a very imprecise estimation of the real runtime. This paper shows a new approach that allows to combine these kinds of simulation to increase the exactness of the estimated time while limiting the additionally required simulation time.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Adve, R.: Direction of arrival estimation (2013)
Binkert, N., Beckmann, B., Black, G., Reinhardt, S.K., Saidi, A., Basu, A., Hestness, J., Hower, D.R., Krishna, T., Sardashti, S., Sen, R., Sewell, K., Shoaib, M., Vaish, N., Hill, M.D., Wood, D.A.: The gem5 simulator. SIGARCH Comput. Archit. News 39(2), 1–7 (2011)
Carlson, T.E., Heirmant, W., Eeckhout, L.: Sniper: exploring the level of abstraction for scalable and accurate parallel multi-core simulation. In: 2011 International Conference for High Performance Computing, Networking, Storage and Analysis (SC), pp. 1–12, November 2011
Cooper, K., Torczon, L.: Engineering a Compiler, 2nd edn. Elsevier, Amsterdam (2012)
Cooper, K.D., Harvey, T.J., Kennedy, K.: A simple, fast dominance algorithm. Softw. Pract. Exp. 4(1–10), 1–8 (2001)
FFmpeg (2017). http://ffmpeg.org/. Accessed 10 2017
Fujimoto, R.: Parallel and distributed simulation. In: Proceedings of the 2015 Winter Simulation Conference, WSC 2015, pp. 45–59. IEEE Press, Piscataway (2015)
Haririan, P., Garcia-Ortiz, A.: Non-intrusive DVFS emulation in gem5 with application to self-aware architectures. In: 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), pp. 1–7, May 2014
Hsieh, M., Pedretti, K., Meng, J., Coskun, A., Levenhagen, M., Rodrigues, A.: SST + gem5 = a scalable simulation infrastructure for high performance computing. In: Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques, SIMUTOOLS 2012, pp. 196–201. ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering), ICST, Brussels (2012)
Joint Collaborative Team on Video Coding: HEVC test model reference software (HM). https://hevc.hhi.fraunhofer.de/, https://hevc.hhi.fraunhofer.de/
Menard, C., Jung, M., Castrillon, J., Wehn, N.: System simulation with gem5 and systemC: the keystone for full interoperability. In: Proceedings of the IEEE International Conference on Embedded Computer Systems Architectures Modeling and Simulation (SAMOS). IEEE, July 2017
Rohling, H.: Radar CFAR thresholding in clutter and multiple target situations. IEEE Trans. Aerosp. Electron. Syst. AES 19(4), 608–621 (1983)
Sullivan, G., Ohm, J., Han, W.J., Wiegand, T.: Overview of the high efficiency video coding (HEVC) standard. IEEE Trans. Circuits Syst. Video Technol. 22(12), 1649–1668 (2012)
Wang, J., Beu, J., Bheda, R., Conte, T., Dong, Z., Kersey, C., Rasquinha, M., Riley, G., Song, W., Xiao, H., Xu, P., Yalamanchili, S.: Manifold: a parallel simulation framework for multicore systems. In: 2014 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp. 106–115, March 2014
Wenger, J.: Automotive radar - status and perspectives. In: IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC 2005, p. 4, October 2005
Winkler, V.: Range doppler detection for automotive FMCW radars. In: 2007 European Microwave Conference, pp. 1445–1448, October 2007
Acknowledgement
This work is supported by the Bavarian Research Foundation (BFS) as part of their research project “FORMUS3IC”.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2018 Springer International Publishing AG, part of Springer Nature
About this paper
Cite this paper
Rachuj, S., Herglotz, C., Reichenbach, M., Kaup, A., Fey, D. (2018). A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Model. In: Berekovic, M., Buchty, R., Hamann, H., Koch, D., Pionteck, T. (eds) Architecture of Computing Systems – ARCS 2018. ARCS 2018. Lecture Notes in Computer Science(), vol 10793. Springer, Cham. https://doi.org/10.1007/978-3-319-77610-1_7
Download citation
DOI: https://doi.org/10.1007/978-3-319-77610-1_7
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-77609-5
Online ISBN: 978-3-319-77610-1
eBook Packages: Computer ScienceComputer Science (R0)