Abstract
Cache memories are a key component of computing systems because they minimize latency between the processor and the main memory. However, they require a large amount of the total energy consumption of the system. This energy demand depends on the application’s behavior. Thus, reconfiguring the cache to fit to every application’s memory requirements with the minimum resources would save a significant amount of energy. This paper presents an architecture that enables the reconfiguration of the cache associativity during runtime, in order to fit the cache to the executing application. The architecture combines the cache ways using a small amount of logic, maintaining the cache entire capacity. We implemented our architecture in a LEON3 processor model and evaluated it using a Xilinx ZC702 FPGA. Our experiments show that the proposed architecture improves upon a way-shutdown approach in terms of energy savings and execution time.
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Acknowledgment
The authors of this paper would like to thank CONACyT (grant number 359472) for its support.
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Navarro, O., Huebner, M. (2018). Runtime Adaptive Cache for the LEON3 Processor. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2018. Lecture Notes in Computer Science(), vol 10824. Springer, Cham. https://doi.org/10.1007/978-3-319-78890-6_28
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DOI: https://doi.org/10.1007/978-3-319-78890-6_28
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