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Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud

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Applied Reconfigurable Computing. Architectures, Tools, and Applications (ARC 2018)

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Abstract

FiC (Flow-in-Cloud)-SW is an FPGA-based switching node for an efficient AI computing system. It is equipped with a number of serial links directly connected to other nodes. Unlike other multi-FPGA systems, the circuit switching fabric with the STDM (Static Time Division Multiplexing) is implemented on the FPGA for predictable communication and cost-efficient data broadcasting. Parallel convolution modules for AlexNet are implemented on FiC-SW1 prototype boards consisting of Kintex Ultrascale FPGA, and evaluation results show that the parallel execution with 20 boards achieved 4.6 times better performance than the state of art implementation on a single Virtex 7 FPGA board.

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References

  1. Tsuruta, C., Miki, Y., Kuhara, T., Amano, H., Umemura, M.: Off-loading LET generation to PEACH2: a switching hub for high performance GPU clusters. In: ACM SIGARCH Computer Architecture News-HEART15, vol. 43, no. 4, April 2016

    Article  Google Scholar 

  2. Koibuchi, M., Anjo, K., Yamada, Y., Jouraku, A., Amano, H.: A simple data transfer technique using local address for netowrks-on-chips. IEEE Trans. Parallel Distrib. Syst. 17(12), 1425–1437 (2006)

    Article  Google Scholar 

  3. Kim, J., Dally, W.J., Scott, S., Abts, D.: Technology-driven, highly-scalable dragonfly topology. In: 2008 35th International Symposium on Computer Architecture. ISCA 2008, pp. 77–88, June 2008

    Google Scholar 

  4. Krizhevsky, A., Sutskever, I., Hinton, G.E.: Imagenet classification with deep convolutional neural networks. In: Advances in Neural Information Processing Systems 25 (2012)

    Google Scholar 

  5. Zhang, C., Li, P., Sun, G., Guan, Y., Xiao, B., Cong, J.: Optimizing FPGA-based accelerator design for deep convolutional neural networks. In: FPGA 2015 Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (2015)

    Google Scholar 

  6. Niu, X.Y., Tsoi, K.H., Luk, W.: Reconfiguring distributed applications in FPGA accelerated cluster with wireless networking. In: The 21st International Conference on Field Programmable Logic ADN Application (FPL), pp. 545–550, September 2011

    Google Scholar 

  7. Muehlbach, S., Koch, A.: A scalable multi-FPGA platform for complex networking applications. In: IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 81–84, May 2011

    Google Scholar 

  8. Moorthy, P., Kapre, N., Zedwulf: power-performance tradeoffs of a 32-node zynq soc cluster. In: IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp. 68–75, May 2015

    Google Scholar 

  9. Sano, K., Hatsuda, Y., Yamamoto, S.: Multi-FPGA accelerator for scalable stencil computation with constant memory bandwidth. IEEE Trans. Parallel Distrib. Syst. 25(3), 695–705 (2013)

    Article  Google Scholar 

  10. Putnum, A., et al.: A reconfigurable fabric for accelerating large-scale datacenter services. In: IEEE/ACM The 41st Annual International Symposium on Computer Architecture (ISCA), pp. 81–84, May 2014

    Google Scholar 

  11. Fukuda, E.S., Inoue, H., Takenaka, T., Kim, D., Sadahira, T., Asai, T., Motomura, M.: Caching memcached at reconfigurable network interface. In: Proceedings of the International Conference on Field Programmable Logic and Application (FPL 2014), September 2014

    Google Scholar 

  12. Hayashi, A., Matsutani, H.: An FPGA-based In-NIC cache approach for lazy learning outlier filtering. In: 25th Euromicro International Conference on Parallel, Distributed and Network-based Processing (PDP), March 2017

    Google Scholar 

  13. Zhang, C., Fang, Z., Zhou, P., Pan, P., Cong, J.: Caffeine: towards uniformed representation and acceleration for deep convolutional neural networks. In: 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (2017)

    Google Scholar 

  14. Ovtcharov, K., Ruwase, O., Kim, J.-Y., Fowers, J., Strauss, K., Chung, E.: Accelerating deep convolutional neural networks using specialized hardware, February 2015

    Google Scholar 

  15. Aydonat, U., O’Connell, S., Capalija, D., Ling, A.C., Chiu, G.R.: An OpenCL(TM) deep learning accelerator on Arria 10. CoRR, abs/1701.03534 (2017)

    Google Scholar 

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Acknowledgements

This paper is based on results obtained from a project commissioned by the New Energy and Industrial Technology Development Organization (NEDO).

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Correspondence to Kazusa Musha .

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Musha, K., Kudoh, T., Amano, H. (2018). Deep Learning on High Performance FPGA Switching Boards: Flow-in-Cloud. In: Voros, N., Huebner, M., Keramidas, G., Goehringer, D., Antonopoulos, C., Diniz, P. (eds) Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2018. Lecture Notes in Computer Science(), vol 10824. Springer, Cham. https://doi.org/10.1007/978-3-319-78890-6_4

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  • DOI: https://doi.org/10.1007/978-3-319-78890-6_4

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