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Formal and Virtual Multi-level Design Space Exploration

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Book cover Model-Driven Engineering and Software Development (MODELSWARD 2017)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 880))

Abstract

With the growing complexity of embedded systems, a systematic design process and tool are vital to help designers assure that their design meets specifications. The design of an embedded system evolves through multiple modeling phases, with varying levels of abstraction. A modeling toolkit should also support the various evaluations needed at each stage, in the form of simulation, formal verification, and performance evaluation. This chapter introduces our model-based engineering process with the supporting toolkit TTool, with two main design stages occurring at a different level of abstraction. A system-level design space exploration selects the architecture and partitions functions into hardware and software. The subsequent software design phase then designs and assesses the detailed functionality of the system, and evaluates the partitioning choices. We illustrate the design phases and supported evaluations with a Smart Card case study.

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References

  1. Apvrille, L.: Webpage of TTool (2015). http://ttool.telecom-paristech.fr/

  2. Genius, D., Li, L.W., Apvrille, L.: Model-driven performance evaluation and formal verification for multi-level embedded system design. In: Conference on Model-Driven Engineering and Software Development (Modelsward 2017), Porto, Portugal (2017)

    Google Scholar 

  3. Buck, J., Ha, S., Lee, E.A., Messerschmitt, D.G.: Ptolemy: a framework for simulating and prototyping heterogeneous systems. In: Readings in Hardware/Software Co-design, pp. 527–543 (2002)

    Chapter  Google Scholar 

  4. Ptolemaeus, C.: System Design, Modeling, and Simulation: Using Ptolemy II. Ptolemy.org, Berkeley (2014)

    Google Scholar 

  5. Kim, H., Guo, L., Lee, E.A., Sangiovanni-Vincentelli, A.: A tool integration approach for architectural exploration of aircraft electric power systems. In: IEEE Proceedings of the 1st International Conference on Cyber-Physical Systems, Networks, and Applications, pp. 38–43. IEEE (2013)

    Google Scholar 

  6. Zimmermann, J., Stattelmann, S., Viehl, A., Bringmann, O., Rosenstiel, W.: Model-driven virtual prototyping for real-time simulation of distributed embedded systems. In: SIES, pp. 201–210. IEEE (2012)

    Google Scholar 

  7. Roth, C., Bucher, H., Reder, S., Buciuman, F., Sander, O., Becker, J.: A SystemC modeling and simulation methodology for fast and accurate parallel MPSoC simulation. In: 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), pp. 1–6. IEEE (2013)

    Google Scholar 

  8. Real, M.M., Wehner, P., Rettkowski, J., Migliore, V., Lapotre, V., Göhringer, D., Gogniat, G.: MPSoCSim extension: an OVP simulator for the evaluation of cluster-based multi and many-core architectures. In: Proceedings of the 4th Workshop on Virtual Prototyping of Parallel and Embedded Systems (ViPES) as Part of the International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XVI), Samos, Greece (2016)

    Google Scholar 

  9. Buchmann, R., Greiner, A.: A fully static scheduling approach for fast cycle accurate SystemC simulation of MPSoCs. In: Proceedings of the ICEEC, Cairo, Egypt, pp. 35–39. IEEE (2007)

    Google Scholar 

  10. Polarsys: ARCADIA/CAPELLA (2008). https://www.polarsys.org/capella/arcadia.html

  11. Lieverse, P., van der Wolf, P., Vissers, K.A., Deprettere, E.F.: A methodology for architecture exploration of heterogeneous signal processing systems. VLSI Signal Process. 29, 197–207 (2001)

    Article  Google Scholar 

  12. Balarin, F., Watanabe, Y., Hsieh, H., Lavagno, L., Passerone, C., Sangiovanni-Vincentelli, A.L.: Metropolis: an integrated electronic system design environment. IEEE Comput. 36, 45–52 (2003)

    Article  Google Scholar 

  13. Erbas, C., Cerav-Erbas, S., Pimentel, A.D.: Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design. IEEE Trans. Evol. Comput. 10, 358–374 (2006)

    Article  Google Scholar 

  14. Kahn, G.: The semantics of a simple language for parallel programming. In: Rosenfeld, J.L. (ed.) Information Processing 1974: Proceedings of the IFIP Congress, pp. 471–475. North-Holland, New York (1974)

    Google Scholar 

  15. Pimentel, A.D., Hertzberger, L.O., Lieverse, P., van der Wolf, P., Deprettere, E.F.: Exploring embedded-systems architectures with Artemis. IEEE Comput. 34, 57–63 (2001)

    Article  Google Scholar 

  16. Kienhuis, B., Deprettere, E.F., van der Wolf, P., Vissers, K.: A methodology to design programmable embedded systems. In: Deprettere, E.F., Teich, J., Vassiliadis, S. (eds.) SAMOS 2001. LNCS, vol. 2268, pp. 18–37. Springer, Heidelberg (2002). https://doi.org/10.1007/3-540-45874-3_2

    Chapter  MATH  Google Scholar 

  17. Vidal, J., de Lamotte, F., Gogniat, G., Soulard, P., Diguet, J.P.: A co-design approach for embedded system modeling and code generation with UML and MARTE. In: DATE 2009, pp. 226–231 (2009)

    Google Scholar 

  18. Gamatié, A., Beux, S.L., Piel, É., Atitallah, R.B., Etien, A., Marquet, P., Dekeyser, J.L.: A model-driven design framework for massively parallel embedded systems. ACM Trans. Embed. Comput. Syst 10, 39 (2011)

    Article  Google Scholar 

  19. Saxena, T., Karsai, G.: MDE-based approach for generalizing design space exploration. In: Petriu, D.C., Rouquette, N., Haugen, Ø. (eds.) MODELS 2010. LNCS, vol. 6394, pp. 46–60. Springer, Heidelberg (2010). https://doi.org/10.1007/978-3-642-16145-2_4

    Chapter  Google Scholar 

  20. Gérard, S., Espinoza, H., Terrier, F., Selic, B.: 6 modeling languages for real-time and embedded systems. In: Giese, H., Karsai, G., Lee, E., Rumpe, B., Schätz, B. (eds.) MBEERTS 2007. LNCS, vol. 6100, pp. 129–154. Springer, Heidelberg (2010). https://doi.org/10.1007/978-3-642-16277-0_6

    Chapter  Google Scholar 

  21. IBM Corporation: Rational Rhapsody. https://www.ibm.com/us-en/marketplace/rational-rhapsody

  22. Sodius Corporation: MDGen for SystemC. http://sodius.com/products-overview/systemc

  23. Feiler, P.H., Lewis, B.A., Vestal, S., Colbert, E.: An overview of the SAE architecture analysis & design language (AADL) standard: a basis for model-based architecture-driven embedded systems engineering. In: Dissaux, P., Filali-Amine, M., Michel, P., Vernadat, F. (eds.) IFIP WCC TC2 2004. IFIP The International Federation for Information Processing, vol. 176, pp. 3–15. Springer, Boston (2004). https://doi.org/10.1007/0-387-24590-1_1

    Chapter  Google Scholar 

  24. Yu, H., Joshi, P., Talpin, J.P., Shukla, S.K., Shiraishi, S.: The challenge of interoperability: model-based integration for automotive control software. In: DAC, pp. 58:1–58:6. ACM (2015)

    Google Scholar 

  25. Bombieri, N., Fummi, F., Vinco, S., Quaglia, D.: Automatic interface generation for component reuse in HW-SW partitioning. In: 2011 14th Euromicro Conference on Digital System Design, pp. 793–796 (2011)

    Google Scholar 

  26. Batori, G., Theisz, Z., Asztalos, D.: Domain specific modeling methodology for reconfigurable networked systems. In: Engels, G., Opdyke, B., Schmidt, D.C., Weil, F. (eds.) MODELS 2007. LNCS, vol. 4735, pp. 316–330. Springer, Heidelberg (2007). https://doi.org/10.1007/978-3-540-75209-7_22

    Chapter  Google Scholar 

  27. Genius, D., Apvrille, L.: Virtual yet precise prototyping: an automotive case study. In: ERTSS 2016, Toulouse (2016)

    Google Scholar 

  28. Genius, D., Apvrille, L.: System-level design for communication-centric task farm applications. In: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, pp. 1–8. IEEE (2017). https://ieeexplore.ieee.org/document/8016145/

  29. Schweppe, H., Roudier, Y., Weyl, B., Apvrille, L., Scheuermann, D.: C2x communication: securing the last meter. In: The 4th IEEE International Symposium on Wireless Vehicular Communications, WIVEC 2011, San Francisco, USA (2011)

    Google Scholar 

  30. SoCLib Consortium: SoCLib: an open platform for virtual prototyping of multi-processors system on chip. http://www.soclib.fr (2010)

  31. VSI Alliance: Virtual component interface standard (OCB 2 2.0). Technical report, VSI Alliance (2000)

    Google Scholar 

  32. Genius, D., Pouillon, N.: Monitoring communication channels on a shared memory multi-processor system on chip. In: ReCoSoC, pp. 1–8. IEEE (2011)

    Google Scholar 

  33. Genius, D., Faure, E., Pouillon, N.: Mapping a telecommunication application on a multiprocessor system-on-chip. In: Gogniat, G., Milojevic, D., Morawiec, A., Erdogan, A. (eds.) Algorithm-Architecture Matching for Signal and Image Processing. LNEE, vol. 73, pp. 53–77. Springer, Dordrecht (2011). https://doi.org/10.1007/978-90-481-9965-5_3

    Chapter  Google Scholar 

  34. Genius, D.: Measuring memory access latency for software objects in a NUMA system-on-chip architecture. In: ReCoSoC, pp. 1–8. IEEE (2013)

    Google Scholar 

  35. Knorreck, D., Apvrille, L., Pacalet, R.: Formal system-level design space exploration. Concurr. Comput.: Pract. Exp. 25, 250–264 (2013)

    Article  Google Scholar 

  36. Enrici, A., Apvrille, L., Pacalet, R.: A model-driven engineering methodology to design parallel and distributed embedded systems. ACM Trans. Des. Autom. Electron. Syst. 22, 34:1–34:25 (2017)

    Article  Google Scholar 

  37. Pedroza, G., Knorreck, D., Apvrille, L.: AVATAR: a SysML environment for the formal verification of safety and security properties. In: The 11th IEEE Conference on Distributed Systems and New Technologies (NOTERE 2011), Paris, France (2011)

    Google Scholar 

  38. Bengtsson, J., Yi, W.: Timed automata: semantics, algorithms and tools. In: Desel, J., Reisig, W., Rozenberg, G. (eds.) ACPN 2003. LNCS, vol. 3098, pp. 87–124. Springer, Heidelberg (2004). https://doi.org/10.1007/978-3-540-27755-2_3

    Chapter  MATH  Google Scholar 

  39. Blanchet, B.: An efficient cryptographic protocol verifier based on prolog rules. In: Proceedings of the 14th IEEE Workshop on Computer Security Foundations, CSFW 2001, Washington, D.C., USA, p. 82. IEEE Computer Society (2001)

    Google Scholar 

  40. Li, L.W., Lugou, F., Apvrille, L.: Security-aware modeling and analysis for HW/SW partitioning. In: Conference on Model-Driven Engineering and Software Development (Modelsward 2017), Porto, Portugal (2017)

    Google Scholar 

  41. Lugou, F., Li, L.W., Apvrille, L., Ameur-Boulifa, R.: SysML models and model transformation for security. In: Conference on Model-Driven Engineering and Software Development (Modelsward 2016), Rome, Italy (2016)

    Google Scholar 

  42. Etienne Faure: Communications matérielles-logicielles dans les systèmes sur puce orientés télécommunications (HW/SW communications in telecommunication oriented MPSoC). Ph.D. thesis, UPMC (2007)

    Google Scholar 

  43. Becoulet, A.: MutekH. http://www.mutekh.org

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Author information

Authors and Affiliations

  1. Télécom ParisTech, Université Paris-Saclay, Biot, France

    Letitia W. Li & Ludovic Apvrille

  2. Sorbonne Universités, UPMC Paris 06, LIP6, CNRS UMR 7606, Paris, France

    Daniela Genius

  3. Institut VEDECOM, Versailles, France

    Letitia W. Li

Authors
  1. Letitia W. Li
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  2. Daniela Genius
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  3. Ludovic Apvrille
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Corresponding authors

Correspondence to Letitia W. Li , Daniela Genius or Ludovic Apvrille .

Editor information

Editors and Affiliations

  1. University of Twente, Enschede, The Netherlands

    Luís Ferreira Pires

  2. Siège du Groupe ESEO, Angers, France

    Slimane Hammoudi

  3. Malina Software Corp., Nepean, Ontario, Canada

    Bran Selic

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Li, L.W., Genius, D., Apvrille, L. (2018). Formal and Virtual Multi-level Design Space Exploration. In: Pires, L., Hammoudi, S., Selic, B. (eds) Model-Driven Engineering and Software Development. MODELSWARD 2017. Communications in Computer and Information Science, vol 880. Springer, Cham. https://doi.org/10.1007/978-3-319-94764-8_3

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  • DOI: https://doi.org/10.1007/978-3-319-94764-8_3

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-94763-1

  • Online ISBN: 978-3-319-94764-8

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