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Approximate Circuits pp 371–382Cite as

Approximate Ultra-Low Voltage Many-Core Processor Design

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Abstract

Computing at ultra-low voltages can increase the energy efficiency significantly, however, operating frequency and resilience to errors degrade as the operating voltage reaches the transistor threshold voltage. More parallelism can help prevent degradation in throughput performance arising from the lower frequency. More parallelism, however, makes more components subject to errors, which exacerbates the already intensified vulnerability to errors. This chapter is all about how to exploit the intrinsic noise tolerance of emerging R(ecognition), M(ining), and S(ynthesis) applications in addressing degraded resilience at ultra-low voltages by embracing errors.

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References

  1. Akturk I, Kim NS, Karpuzcu UR (2015) Decoupled control and data processing for approximate near-threshold voltage computing. IEEE Micro 35(4):70–78

    Article  Google Scholar 

  2. Bhadauria M, Weaver VM, McKee SA (2009) Understanding PARSEC performance on contemporary CMPs. In: Proceedings of the IEEE International Symposium on Workload Characterization (IISWC), Washington, DC, USA, pp 98–107

    Google Scholar 

  3. Bienia C (January 2011) Benchmarking modern multiprocessors. Ph.D. Thesis, Princeton University

    Google Scholar 

  4. Chang L et al (February 2010) Practical strategies for power-efficient computing technologies. Proc IEEE 98(2):215–236

    Google Scholar 

  5. Chippa VK, Mohapatra D, Raghunathan A, Roy K, Chakradhar ST (2010) Scalable effort hardware design: exploiting algorithmic resilience for energy efficiency. In: ACM/EDAC/IEEE design automation conference

    Google Scholar 

  6. Chippa V, Raghunathan A, Roy K, Chakradhar S (2011) Dynamic effort scaling: managing the quality-efficiency tradeoff. In: ACM/EDAC/IEEE design automation conference

    Google Scholar 

  7. Cho H, Leem L, Mitra S (April 2012) ERSA: Error Resilient System Architecture for probabilistic applications. In: IEEE Trans Comput Aided Des Integr Circuits Syst 31(4):546–558

    Google Scholar 

  8. de Kruijf M, Nomura S, Sankaralingam K (2011) Relax: an architectural framework for software recovery of hardware faults. In: IEEE/ACM International Symposium on Computer Architecture (ISCA)

    Google Scholar 

  9. Dennard RH, Gaensslen FH, Rideout VL, Bassous E, LeBlanc AR (October 1974) Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J Solid State Circuits 9(5):256–268

    Article  Google Scholar 

  10. Dreslinski RG, Wieckowski M, Blaauw D, Sylvester D, Mudge T (February 2010) Near-threshold computing: reclaiming Moore’s law through energy efficient integrated circuits. Proc IEEE 98(2):253–266

    Article  Google Scholar 

  11. Dreslinski RG, Giridhar B, Pinckney N, Blaauw D, Sylvester D, Mudge T (2012) Reevaluating fast dual-voltage power rail switching circuitry. In: Annual Workshop of Duplicating, Deconstructing and Debunking (WDDD) in conjunction with ISCA, vol. 39

    Google Scholar 

  12. Esmaeilzadeh H, Sampson A, Ceze L, Burger D (2012) In: ACM international conference on architectural support for programming languages and operating systems

    Google Scholar 

  13. Greskamp B et al (2009) Blueshift: designing processors for timing speculation from the ground up. In: IEEE international symposium on high performance computer architecture

    Google Scholar 

  14. Gustafson JL (1988) Reevaluating Amdahl’s law. Commun ACM 31(5):532–533

    Article  Google Scholar 

  15. Horowitz M (2014) Computing’s energy problem (and what we can do about it). In: Keynote at IEEE international conference on solid state circuits

    Google Scholar 

  16. Jain S et al (2012) A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. In: IEEE international solid-state circuits conference, San Francisco, CA, pp 66–68

    Google Scholar 

  17. Kaul H, Anders M, Hsu S, Agarwal A, Krishnamurthy R, Borkar S (2012) Near-threshold voltage (NTV) design – opportunities and challenges. In: ACM/EDAC/IEEE design automation conference

    Google Scholar 

  18. Karpuzcu UR, Kolluru KB, Kim NS, Torrellas J (2012) VARIUS-NTV: a microarchitectural model to capture the increased sensitivity of manycores to process variations at near-threshold voltages. In: IEEE/IFIP international conference on dependable systems and networks

    Google Scholar 

  19. Karpuzcu UR, Sinkar A, Kim NS, Torrellas J (2013) EnergySmart: toward energy-efficient manycores for near-threshold computing. IEEE international symposium on High Performance Computer Architecture (HPCA), Shenzhen, pp 542–553

    Google Scholar 

  20. Karpuzcu UR, Akturk I, Kim NS (2014) Accordion: toward soft near-threshold voltage computing. IEEE international symposium on High Performance Computer Architecture (HPCA), Orlando, FL, pp 72–83

    Google Scholar 

  21. Patel J (2008) CMOS process variations: a critical operation point hypothesis. https://web.stanford.edu/class/ee380/Abstracts/080402-jhpatel.pdf

  22. Snyder L (1986) Type architectures, shared memory, and the corollary of modest potential. In: Traub JF, Grosz BJ, Lampson BW, Nilsson NJ (eds.) Annual review of computer science, vol 1. Annual Reviews Inc., Palo Alto, pp 289–317

    Google Scholar 

  23. Taylor M (2012) Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse. In: ACM/EDAC/IEEE design automation conference

    Google Scholar 

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Author information

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Illinois, Urbana Champaign, IL, USA

    Nam Sung Kim

  2. Department of Electrical and Computer Engineering, University of Minnesota, Twin Cities, MN, USA

    Ulya R. Karpuzcu

Authors
  1. Nam Sung Kim
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  2. Ulya R. Karpuzcu
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Corresponding author

Correspondence to Ulya R. Karpuzcu .

Editor information

Editors and Affiliations

  1. Brown University, Rhode Island, Providence, USA

    Sherief Reda

  2. Vienna University of Technology, Wien, Wien, Austria

    Muhammad Shafique

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Kim, N.S., Karpuzcu, U.R. (2019). Approximate Ultra-Low Voltage Many-Core Processor Design. In: Reda, S., Shafique, M. (eds) Approximate Circuits. Springer, Cham. https://doi.org/10.1007/978-3-319-99322-5_18

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  • DOI: https://doi.org/10.1007/978-3-319-99322-5_18

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  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-319-99321-8

  • Online ISBN: 978-3-319-99322-5

  • eBook Packages: EngineeringEngineering (R0)

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