Garbage-Free Reversible Multiplication and Division

Abstract

We present a circuit design for garbage-free reversible multiplier. Given inputs $A,\,B$ and R, where $0\le B < 2^m$ and $0\le R<A<2^n$, the circuit outputs A and $P = A\cdot B+R$. Applied in reverse, the circuit takes as input A and P, where $0<A<2^n$ and $0\le P< 2^mA$, and outputs A, $B = P/A$ and $R = P\%A$. The circuit uses a total of two ancilla bits.

The circuit is constructed as a sequence of m modified ripple-carry adders and comparators, both of which have O(n) gate delay, so the multiplier has O($m\times n$) gate delay, but this can be improved to O($m\times \log (n)$) by using a modified carry-lookahead adder and an O($\log (n)$) comparator, both of which are described in the paper. The cost of reducing the gate delay to O($m\times \log (n)$) is O(n) added ancilla bits and a larger gate count.

This work was partially supported by the European COST Action IC 1405: Reversible Computation - Extending Horizons of Computing.