Abstract
In the paper, we propose a new method for FPGA-based design of high-speed Algorithmic State Machine (ASM) controllers. The method is based on the introduction of additional states of the state machine in order to implement all transition functions in the single-level structures. In this method, such an optimization criterion as a critical path delay is applied already at the stage of converting the ASM chart to the state machine HDL description. The proposed method consists of two steps: determining the place of additional labels on the ASM chart and introducing additional states of FSM. Experimental results show that our approach achieves an average performance gain of 20.43% to 27.41% (for various FPGA devices) compared with the traditional synthesis method. The maximum performance increase achieved is 59.17%. At the same time, the method slightly increases the cost of implementation by an average of 5.13% to 5.19%, but in some cases even reduces the cost.
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This work was supported by grant S/WI/3/2018 (from the Bialystok University of Technology, Bialystok, Poland) founded by the Polish Ministry of Science and Higher Education.
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Salauyou, V., Bulatowa, I. (2018). Synthesis of High-Speed ASM Controllers with Moore Outputs by Introducing Additional States. In: Saeed, K., Homenda, W. (eds) Computer Information Systems and Industrial Management. CISIM 2018. Lecture Notes in Computer Science(), vol 11127. Springer, Cham. https://doi.org/10.1007/978-3-319-99954-8_34
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DOI: https://doi.org/10.1007/978-3-319-99954-8_34
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