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Low-Power Design of a Functional Unit for Arithmetic in Finite Fields GF(p) and GF(2m)

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Book cover Information Security Applications (WISA 2003)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2908))

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Abstract

Recent multi-application smart cards are equipped with powerful 32-bit RISC cores clocked at 33 MHz or even more. They are able to support a variety of public-key cryptosystems, including elliptic curve systems over prime fields GF(p) and binary fields GF(2m) of arbitrary order. This flexibility is achieved by implementing the cryptographic primitives in software and taking advantage of dedicated instruction set extensions along with special functional units for low-level arithmetic operations. In this paper, we present the design of a low-power multiply/accumulate (MAC) unit for efficient arithmetic in finite fields. The MAC unit combines integer arithmetic and polynomial arithmetic into a single functional unit which can be configured at run-time to serve both types of fields, GF(p) and GF(2m). Our experimental results show that a properly designed unified (dual-field) multiplier consumes significantly less power in polynomial mode than in integer mode.

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References

  1. ARM Limited. ARM SecurCore Solutions. Product brief (2002), available for download at http://www.arm.com/aboutarm/4XAFLB/$File/SecurCores.pdf

  2. Au, L.-S., Burgess, N.: A (4:2) adder for unified GF(p) and GF(2n) Galois field multipliers. In: Conference Record of the 36th Asilomar Conference on Signals, Systems, and Computers, vol. 2, pp. 1619–1623. IEEE, Los Alamitos (2002)

    Google Scholar 

  3. Blake, I.F., Seroussi, G., Smart, N.P.: Elliptic Curves in Cryptography. Cambridge University Press, Cambridge (1999)

    MATH  Google Scholar 

  4. Bucci, M.: Dual mode (integer, polynomial) fast modular multipliers. Presentation at the Rump Session of EUROCRYPT 1997, Konstanz, Germany, May 13 (1997)

    Google Scholar 

  5. Dhem, J.-F.: Efficient modular reduction algorithm in \(\mathbb{F}_{q}[{\it x}]\) and its application to “left to right” modular multiplication in \(\mathbb{F}_{2}[{\it x}]\). In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 203–213. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  6. Drescher, W., Bachmann, K., Fettweis, G.: VLSI architecture for datapath integration of arithmetic over GF(\(2^{\it m}\)) on digital signal processors. In: Proceedings of the 22nd IEEE Int. Conference on Acoustics, Speech, and Signal Processing (ICASSP 1997), vol. 1, pp. 631–634. IEEE, Los Alamitos (1997)

    Chapter  Google Scholar 

  7. Farooqui, A.A., Oklobdžija, V.G.: General data-path organization of a MAC unit for VLSI implementation of DSP processors. In: Proceedings of the 31st IEEE Int. Symposium on Circuits and Systems (ISCAS 1998), vol. 2, pp. 260–263. IEEE, Los Alamitos (1998)

    Google Scholar 

  8. Goodman, J.R., Chandrakasan, A.P.: An energy efficient reconfigurable publickey cryptography processor architecture. In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 175–190. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  9. Großschädl, J.: A unified radix-4 partial product generator for integers and binary polynomials. In: Proceedings of the 35th IEEE Int. Symposium on Circuits and Systems (ISCAS 2002), vol. 3, pp. 567–570. IEEE, Los Alamitos (2002)

    Google Scholar 

  10. Großschädl, J., Kamendje, G.-A.: Instruction set extension fast elliptic curve cryptography over binary finite fields GF(\(2^{\it m}\)). In: Proceedings of the 14th IEEE Int. Conference on Application-specific Systems, Architectures and Processors (ASAP 2003), pp. 455–468. IEEE Computer Society Press, Los Alamitos (2003)

    Chapter  Google Scholar 

  11. Großschädl, J., Kamendje, G.-A.: A single-cycle (32×32+32+64)-bit multiply/accumulate unit for digital signal processing and public-key cryptography. Accepted for presentation at the 10th IEEE Int. Conference on Electronics, Circuits and Systems (ICECS 2003), scheduled for December 14-17, in Sharjah, U.A.E. (2003)

    Google Scholar 

  12. Handschuh, H., Paillier, P.: Smart card crypto-coprocessors for public-key cryptography. In: Schneier, B., Quisquater, J.-J. (eds.) CARDIS 1998. LNCS, vol. 1820, pp. 372–379. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  13. Huang, Z.: High-Level Optimization Techniques for Low-Power Multiplier Design. Ph.D. Thesis, University of California, Los Angeles, CA, USA (2003)

    Google Scholar 

  14. Koç, Ç.K., Acar, T.: Montgomery multiplication in GF(2k). Designs, Codes and Cryptography 14(1), 57–69 (1998)

    Article  MATH  MathSciNet  Google Scholar 

  15. MacSorley, O.L.: High-speed arithmetic in binary computers. Proceedings of the IRE 49(1), 67–91 (1961)

    Article  MathSciNet  Google Scholar 

  16. Mekhallalati, M.C., Ashur, A.S., Ibrahim, M.K.: Novel radix finite field multiplier for GF(\(2^{\it m}\)). Journal of VLSI Signal Processing 15(3), 233–245 (1997)

    Article  Google Scholar 

  17. MIPS Technologies, Inc. MIPS32 4KmTM processor core family data sheet (2001), Available for download at http://www.mips.com/publications/index.html

  18. MIPS Technologies, Inc. SmartMIPS Architecture Smart Card Extensions (2001), Product brief available for download at http://www.mips.com/ProductCatalog/P_SmartMIPSASE/SmartMIPS.pdf

  19. Nahum, E.M., O’Malley, S.W., Orman, H.K., Schroeppel, R.C.: Towards high performance cryptographic software. In: Proceedings of the 3rd IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems (HPCS 1995), pp. 69–72. IEEE, Los Alamitos (1995)

    Chapter  Google Scholar 

  20. Oklobdžija, V.G.: Design and analysis of fast carry-propagate adder under nonequal input signal arrival profile. In: Conference Record of the 28th Asilomar Conference on Signals, Systems, and Computers, vol. 2, pp. 1398–1401. IEEE, Los Alamitos (1994)

    Google Scholar 

  21. Oklobdžija, V.G., Villeger, D., Liu, S.S.: A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approach. IEEE Transactions on Computers 45(3), 294–306 (1996)

    Article  MATH  Google Scholar 

  22. Parhami, B.: Computer Arithmetic: Algorithms and Hardware Designs. Oxford University Press, Oxford (2000)

    Google Scholar 

  23. Rabaey, J.M.: Digital Integrated Circuits – A Design Perspective. Prentice Hall, Englewood Cliffs (1996)

    Google Scholar 

  24. Salomon, O., Green, J.-M., Klar, H.: General algorithms for a simplified addition of 2’s complement numbers. IEEE Journal of Solid-State Circuits 30(7), 839–844 (1995)

    Article  Google Scholar 

  25. Satoh, A., Takano, K.: A scalable dual-field elliptic curve cryptographic processor. IEEE Transactions on Computers 52(4), 449–460 (2003)

    Article  Google Scholar 

  26. Savaş, E., Tenca, A.F., Koç, Ç.K.: A scalable and unified multiplier architecture for finite fields GF(p) and GF(2m). In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 277–292. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

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Großschädl, J., Kamendje, GA. (2004). Low-Power Design of a Functional Unit for Arithmetic in Finite Fields GF(p) and GF(2m). In: Chae, KJ., Yung, M. (eds) Information Security Applications. WISA 2003. Lecture Notes in Computer Science, vol 2908. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24591-9_18

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  • DOI: https://doi.org/10.1007/978-3-540-24591-9_18

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-20827-3

  • Online ISBN: 978-3-540-24591-9

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