Abstract
Redundancy identification is a challenging open problem in logic optimization of Boolean circuits. Partitioning techniques are employed successfully to solve the redundancy identification problem with less time and higher scalability. Any heuristic/algorithm for the Logic optimization problem, and hence the redundancy identification problem is compute-intensive, especially when very high approximation to the optimal solution is demanded. This is because the problems are NP-complete. This necessitates parallel heuristics/algorithms to speed-up the computation process. In this paper, we present a parallel partitioning approach for the logic optimization problem using the concept of redundancy identification. This result finds extensive applications in the area of VLSI CAD tool design.
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Jayaram, B., Kumar, A.M., Kamakoti, V. (2003). Parallel Partitioning Techniques for Logic Minimization Using Redundancy Identification. In: Pinkston, T.M., Prasanna, V.K. (eds) High Performance Computing - HiPC 2003. HiPC 2003. Lecture Notes in Computer Science, vol 2913. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24596-4_19
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DOI: https://doi.org/10.1007/978-3-540-24596-4_19
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20626-2
Online ISBN: 978-3-540-24596-4
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