Skip to main content
SpringerLink
Log in

Reasoning about Infinite State Systems Using Boolean Methods

  • Conference paper
Book cover FST TCS 2003: Foundations of Software Technology and Theoretical Computer Science (FSTTCS 2003)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2914))

  • 384 Accesses

Abstract

The logic of Counters, Lambdas, and Uninterpreted functions (CLU) is a subset of first-order logic satisfying the twin properties that 1) the validity of a CLU formula can be decided by generating a Boolean formula and using a Boolean satisfiability (SAT) checker to show the formula is unsatisfiable, and 2) it has sufficient expressive power to construct models of a variety of interesting software and hardware systems. We describe this logic and show its modeling capabilities.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Barrett, C., Dill, D., Levitt, J.: Validity checking for combinations of theories with equality. In: Srivas, M., Camilleri, A. (eds.) FMCAD 1996. LNCS, vol. 1166, pp. 187–201. Springer, Heidelberg (1996)

    Chapter  Google Scholar 

  2. Bryant, R.E., German, S., Velev, M.N.: Exploiting positive equality in a logic of equality with uninterpreted functions. In: Halbwachs, N., Peled, D.A. (eds.) CAV 1999. LNCS, vol. 1633, pp. 470–482. Springer, Heidelberg (1999)

    Chapter  Google Scholar 

  3. Bryant, R.E., Lahiri, S.K., Seshia, S.A.: Modeling and verifying systems using a logic of counter arithmetic with lambda expressions and uninterpreted functions. In: Brinksma, E., Larsen, K.G. (eds.) CAV 2002. LNCS, vol. 2404, pp. 78–92. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  4. Bultan, T., Gerber, R., Pugh, W.: Symbolic model checking of infinite state systems using Presburger arithmetic. In: Grumberg, O. (ed.) CAV 1997. LNCS, vol. 1254, pp. 400–411. Springer, Heidelberg (1997)

    Google Scholar 

  5. Burch, J.R., Clarke, E.M., McMillan, K.L., Dill, D.L.: Sequential circuit verification using symbolic model checking. In: 27th Design Automation Conference (DAC 1990), pp. 46–51 (1990)

    Google Scholar 

  6. Burch, J.R., Dill, D.L.: Automated verification of pipelined microprocessor control. In: Dill, D.L. (ed.) CAV 1994. LNCS, vol. 818, pp. 68–80. Springer, Heidelberg (1994)

    Google Scholar 

  7. Clarke, E.M., Biere, A., Raimi, R., Zhu, Y.: Bounded model checking using satisfiability solving. Formal Methods in System Design 19(1), 7–34 (2001)

    Article  MATH  Google Scholar 

  8. German, S.: Personal communication

    Google Scholar 

  9. Graf, S., Saïdi, H.: Construction of abstract state graphs with PVS. In: Grumberg, O. (ed.) CAV 1997. LNCS, vol. 1254, pp. 72–83. Springer, Heidelberg (1997)

    Google Scholar 

  10. Hosabettu, R., Gopalakrishnan, G., Srivas, M.: Proof of correctness of a processor with reorder buffer using the completion function approach. In: Halbwachs, N., Peled, D.A. (eds.) CAV 1999. LNCS, vol. 1633, pp. 47–59. Springer, Heidelberg (1999)

    Chapter  Google Scholar 

  11. Lahiri, S.K., Seshia, S.A., Bryant, R.E.: Modeling and verification of out-oforder microprocessors in UCLID. In: Aagaard, M.D., O’Leary, J.W. (eds.) FMCAD 2002. LNCS, vol. 2517, pp. 142–159. Springer, Heidelberg (2002)

    Chapter  Google Scholar 

  12. Lahiri, S.K., Bryant, R.E.: Deductive verification of advanced out-of-order microprocessors. In: Hunt Jr., W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, pp. 341–354. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  13. Lahiri, S.K., Bryant, R.E., Cook, B.: A symbolic approach to predicate abstraction. In: Hunt Jr., W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, pp. 141–153. Springer, Heidelberg (2003)

    Chapter  Google Scholar 

  14. Lamport, L.: A new solution of Dijkstra’s concurrent programming problem. Communications of the ACM 17, 453–455 (1974)

    Article  MATH  MathSciNet  Google Scholar 

  15. McMillan, K.: A methodology for hardware verification using compositional model checking. Science of Computer Programming 37(1-3), 279–309 (2000)

    Article  MATH  Google Scholar 

  16. Moskewicz, M., Madigan, C., Zhao, Y., Zhang, L., Malik, S.: Chaff: Engineering an efficient SAT solver. In: 38th Design Automation Conference (DAC 2001), pp. 530–535 (2001)

    Google Scholar 

  17. Pnueli, A., Ruah, S., Zuck, L.: Automatic deductive verification with invisible invariants. In: Margaria, T., Yi, W. (eds.) TACAS 2001. LNCS, vol. 2031, pp. 82–97. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  18. Sawada, J., Hunt Jr., W.A.: Processor verification with precise exceptions and speculative execution. In: Y. Vardi, M. (ed.) CAV 1998. LNCS, vol. 1427, pp. 135–146. Springer, Heidelberg (1998)

    Chapter  Google Scholar 

  19. Sistla, A.P., German, S.M.: Reasoning about systems with many processes. J. ACM 39, 675–735 (1992)

    Article  MATH  MathSciNet  Google Scholar 

  20. Velev, M.N., Bryant, R.E.: Effective use of Boolean satisfiability procedures in the formal verification of superscalar and VLIW microprocessors. In: 38th Design Automation Conference (DAC 2001), pp. 226–231 (2001)

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Computer Science Department, Carnegie Mellon University, Pittsburgh, PA, USA

    Randal E. Bryant

Authors
  1. Randal E. Bryant
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Tata Institute of Fundamental Research, India

    Paritosh K. Pandya

  2. Tata Institute of Fundamental Research, School of Technology and Computer Science, Mumbai, India

    Jaikumar Radhakrishnan

Rights and permissions

Reprints and permissions

Copyright information

© 2003 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Bryant, R.E. (2003). Reasoning about Infinite State Systems Using Boolean Methods. In: Pandya, P.K., Radhakrishnan, J. (eds) FST TCS 2003: Foundations of Software Technology and Theoretical Computer Science. FSTTCS 2003. Lecture Notes in Computer Science, vol 2914. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24597-1_34

Download citation

  • DOI: https://doi.org/10.1007/978-3-540-24597-1_34

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-20680-4

  • Online ISBN: 978-3-540-24597-1

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation