Abstract
Application energy consumption has become an increasingly important issue for both high-end microprocessors and mobile and embedded devices. A multitude of circuit and architecture-level techniques have been developed to improve application energy efficiency. However, relatively less work studies the effects of compiler transformations in terms of application energy efficiency. In this paper, we use energy-estimation tools to profile the execution of benchmark applications. The results show that energy consumption due to memory instructions accounts for a large share of total energy. An effective compiler technique that can improve energy efficiency is memory redundancy elimination. It reduces both application execution cycles and the number of cache accesses. We evaluate the energy improvement over 12 benchmark applications from SPEC2000 and MediaBench. The results show that memory redundancy elimination can significantly reduce energy in the processor clocking network and the instruction and data caches. The overall application energy consumption can be reduced by up to 15%, and the reduction in terms of energy-delay product is up to 24%.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Pering, T., et al.: The simulation and evaluation of dynamic voltage scaling algorithms. In: Int. Symp. on Low Power Electronics and Design, pp. 76–81 (1998)
Ghose, K., Kamble, M.: Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation. In: Int. Symp. on Low Power Electronics and Design, pp. 70–75 (1999)
Kin, J., et al.: The filter cache: An energy efficient memory structure. In: Int. Symp. on Microarchitecture, pp. 184–193 (1997)
Simunic, T., Benini, L., Acquaviva, A., Glynn, P., Micheli, G.D.: Dynamic voltage scaling for portable systems. In: Design Automation Conf. (2001)
Lorch, J.R., Smith, A.J.: Improving dynamic voltage scaling algorithms with PACE. In: SIGMETRICS/Performance, pp. 50–61 (2001)
Albonesi, D.H.: Selective cache ways: On-demand cache resource allocation. In: International Symp. on Microarchitecture (1999)
Allen, R., Kennedy, K.: Optimizing Compilers for Modern Architectures: A Dependence-based Approach. Morgan Kaufmann, San Francisco (2002)
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a framework for architectural-level power analysis and optimizations. In: ISCA, pp. 83–94 (2000)
Ye, W., Vijaykrishnan, N., Kandemir, M.T., Irwin, M.J.: The design and use of simplepower: a cycle-accurate energy estimation tool. In: Design Automation Conf., pp. 340–345 (2000)
Burger, D., Austin, T.: The simplescalar toolset, version 2.0. Computer Architecture News, pp. 13–25 (1997)
Gonzalez, R., Horowitz, M.: Energy dissipation in general purpose microprocessors. IEEE Journal of Solid-State Circuits, 1277–1283 (1996)
Lee, C., Potkonjak, M., Mangione-Smith, W.H.: Mediabench: A tool for evaluating and synthesizing multimedia and communications systems. In: Int. Symp. on Microarchitecture, pp. 330–335 (1997)
Cooper, K.D., Xu, L.: An efficient static analysis algorithm to detect redundant memory operations. In: ACM Workshop on Memory Systems Performance (2002)
Simpson, T.: Value-Driven Redundancy Elimination. PhD thesis, Rice U (1996)
Gargi, K.: A sparse algorithm for predicated global value numbering. In: ACM SIGPLAN PLDI, pp. 45–56 (2002)
Andersen, L.O.: Program Analysis and Specialization for the C Programming Language. PhD thesis, University of Copenhagen (1994)
Cocke, J.: Global common subexpression elimination. In: Symp. on Compiler Construction, pp. 20–24 (1970)
Morel, E., Renvoise, C.: Global optimization by suppression of partial redundancies. Commun. ACM, 96–103 (1979)
Knoop, J., Rüthing, O., Steffen, B.: Lazy code motion. In: ACM SIGPLAN PLDI, pp. 224–234 (1992)
Drechsler, K.H., Stadel, M.P.: A variation of knoop, ruthing, and steffen’s lazy code motion. SIGPLAN Notices, 29–38 (1993)
Xu, L.: Program Redundancy Analysis and Optimization to Improve Memory Performance. PhD thesis, Rice University (2003)
Kandemir, M.T., Vijaykrishnan, N., et al.: Influence of compiler optimizations on system power. In: Design Automation Conf., pp. 304–307 (2000)
Hsu, C.H., Kremer, U.: The design, implementation, and evaluation of a compiler algorithm for cpu energy reduction. In: ACM SIGPLAN PLDI, pp. 38–48 (2003)
Kremer, U.: Compilers for power and energy management. PLDI Tutorial (2003)
Briggs, P., Cooper, K.D., Simpson, L.T.: Value numbering. Software: Practice and Experience, 710–724 (1977)
Lu, J., Cooper, K.: Register promotion in c programs. In: ACM SIGPLAN PLDI, pp. 308–319 (1997)
Lo, R., Chow, F., Kennedy, R., Liu, S.M., Tu, P.: Register promotion by sparse partial redundancy elimination of loads and stores. In: ACM SIGPLAN PLDI, pp. 26–37 (1998)
Sastry, A., Ju, R.D.: A new algorithm for scalar register promotion based on ssa form. In: ACM SIGPLAN PLDI, pp. 15–25 (1998)
Bodik, R., Gupta, R., Soffa, M.L.: Load-reuse analysis: Design and evaluation. In: ACM SIGPLAN PLDI, pp. 64–76 (1999)
Callahan, D., Carr, S., Kennedy, K.: Improving register allocation for subscripted variables. In: ACM SIGPLAN PLDI, pp. 53–65 (1990)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Cooper, K.D., Xu, L. (2004). Memory Redundancy Elimination to Improve Application Energy Efficiency. In: Rauchwerger, L. (eds) Languages and Compilers for Parallel Computing. LCPC 2003. Lecture Notes in Computer Science, vol 2958. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24644-2_19
Download citation
DOI: https://doi.org/10.1007/978-3-540-24644-2_19
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-21199-0
Online ISBN: 978-3-540-24644-2
eBook Packages: Springer Book Archive