Abstract
Hash functions are among the most widespread cryptographic primitives, and are currently used in multiple cryptographic schemes and security protocols, such as IPSec and SSL. In this paper, we investigate a new hardware architecture for a family of dedicated hash functions, including American standards SHA-1 and SHA-512. Our architecture is based on unrolling several message digest steps and executing them in one clock cycle. This modification permits implementing majority of dedicated hash functions with the throughput exceeding 1 Gbit/s using medium-size Xilinx Virtex FPGAs. In particular, our new architecture has enabled us to speed up the implementation of SHA-1 compared to the basic iterative architecture from 544 Mbit/s to 1 Gbit/s using Xilinx XCV1000. The implementation of SHA-512 has been sped up from 717 to 929 Mbit/s for Virtex FPGAs, and exceeded 1 Gbit/s for Virtex-E Xilinx FPGAs.
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References
NIST Cryptographic Toolkit, available at http://csrc.nist.gov/CryptoToolkit/
Xilinx, Inc.: Virtex 2.5 V Field Programmable Gate Arrays, available at http://www.xilinx.com
ALMA Technologies web page, available at http://www.alma-tech.com
Amphion Semiconductor web page, available at http://www.amphion.com
Bisquare Systems Private Limited web page, available at http://www.bisquare.com
Helion Technology Limited web page, available at http://www.heliontech.com
Intron, Ltd. Web page, available at http://www.intron.lviv.ua
Ocean Logic Pty Ltd web page, available at http://www.ocean-logic.com
Grembowski, T., Lien, R., Gaj, K., Nguyen, N., Bellows, P., Flidr, J., Lehman, T., Schott, B.: Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512. In: Chan, A.H., Gligor, V.D. (eds.) ISC 2002. LNCS, vol. 2433, pp. 75–89. Springer, Heidelberg (2002)
Bellows, P., Flidr, J., Gharai, L., Perkins, C., Chodowiec, P., Gaj, K.: IPsec-Protected Transport of HDTV over IP. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 869–879. Springer, Heidelberg (2003)
Deepakumara, J., Heys, H.M., Venkatesan, R.: FPGA Implementation of MD5 Hash Algorithm. In: Proc. IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2001), Toronto, Ontario (May 2001), available at http://www.engr.mun.ca/~howard/PAPERS/ccece_2001.pdf
Hoare, R., Menon, P., Ramos, M.: 427 Mbits/sec Hardware Implementation of the SHA-1 Algorithm in an FPGA, International Association of Science and Technology for Development (IASTED) Journal (2002)
Ting, K.K., Yuen, S.C.L., Lee, K.H., Leong, P.H.W.: An FPGA Based SHA-256 Processor. In: Glesner, M., Zipf, P., Renovell, M. (eds.) FPL 2002. LNCS, vol. 2438, p. 577. Springer, Heidelberg (2002)
Kang, K.Y., Kim, D.W., Kwon, T.W., Choi, J.R.: Hash Function Processor Using Resource Sharing for IPSec, In: Proc. International Technical Conference On Circuit/ Systems, Computers and Communications (2002)
Crypto++, free C++ class library of cryptographic schemes, available at http://www.eskimo.com/~weidai/cryptlib.html
Digital Signature Standard Validation System (DSSVS) User’s Guide, available at http://csrc.nist.gov/cryptval/shs.html
McCurley, K.S.: A Fast Portable Implementation of the Secure Hash Algorithm, Sandia National Laboratories Technical Report SAND93–2591
Bosselaers, A., Govaerts, R., Vandewalle, J.: Fast Hashing on the Pentium. In: Koblitz, N. (ed.) CRYPTO 1996. LNCS, vol. 1109, pp. 298–312. Springer, Heidelberg (1996)
Bosselaers, A., Govaerts, R., Vandewalle, J.: SHA: A Design for Parallel Architectures? In: Fumy, W. (ed.) EUROCRYPT 1997. LNCS, vol. 1233, pp. 348–362. Springer, Heidelberg (1997)
Nakajima, J., Matsui, M.: Performance Analysis and Parallel Implementation of Dedicated Hash Functions. In: Knudsen, L.R. (ed.) EUROCRYPT 2002. LNCS, vol. 2332, pp. 165–180. Springer, Heidelberg (2002)
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Lien, R., Grembowski, T., Gaj, K. (2004). A 1 Gbit/s Partially Unrolled Architecture of Hash Functions SHA-1 and SHA-512. In: Okamoto, T. (eds) Topics in Cryptology – CT-RSA 2004. CT-RSA 2004. Lecture Notes in Computer Science, vol 2964. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24660-2_25
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DOI: https://doi.org/10.1007/978-3-540-24660-2_25
Publisher Name: Springer, Berlin, Heidelberg
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