Abstract
Coarse-grain reconfigurable processors become more and more an alternative to FPGA based fine-grain reconfigurable devices due to their reduction of configuration overhead. This provides a higher degree of flexibility for dynamically reconfigurable systems design. But, to make them more interesting for industrial applications, suitable frameworks supporting design space exploration as well as the automatic generation of dedicated design tools are still missing.
In our paper we present a runtime-reconfigurable VLIW processor which combines hardwired and reconfigurable functional units in one template. For design space exploration, we discuss a framework, called RECAST (Reconfiguration-Enabled Compiler And Simulation Toolset), based on a architecture description language, which is extended by a model of coarse-grain runtime-reconfigurable units. The framework comprises a retargetable compiler based on the SUIF compiler kit, a profiler driven hardware/software partitioner and a retargetable simulator.
To evaluate the framework we performed some experiments on a instance of the architecture template. The results show an increase in performance but also a lot of potential for further improvements.
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Braunes, J., Köhler, S., Spallek, R.G. (2004). RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures. In: Müller-Schloer, C., Ungerer, T., Bauer, B. (eds) Organic and Pervasive Computing – ARCS 2004. ARCS 2004. Lecture Notes in Computer Science, vol 2981. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24714-2_13
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DOI: https://doi.org/10.1007/978-3-540-24714-2_13
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