Abstract
This paper presents a new digit-serial systolic multiplier over GF(2m) for cryptographic applications. When input data come in continuously, the proposed array produces multiplication results at a rate of one every ⌈m/D ⌉ +2 clock cycles, where D is the selected digit size. Since the inner structure of the proposed array is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementations.
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Kim, C.H., Kwon, S., Hong, C.P., Kim, H. (2004). A New Systolic Array for Least Significant Digit First Multiplication in GF(2m). In: Laganá, A., Gavrilova, M.L., Kumar, V., Mun, Y., Tan, C.J.K., Gervasi, O. (eds) Computational Science and Its Applications – ICCSA 2004. ICCSA 2004. Lecture Notes in Computer Science, vol 3045. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-24767-8_69
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DOI: https://doi.org/10.1007/978-3-540-24767-8_69
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22057-2
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