Abstract
This paper describes our state-of-the-art design flow used for specification, implementation and verification of a 10 million gates ASIC System-on-Chip (SoC) for a Sonet/SDH application. We present our tools and methodologies currently used and/or being developed for a multisite ASIC design project from the first specification up to the gate level netlist: our multi-site data management environment VHDLDevSys, our multi-use and re-use library ADK-Lib and our multi-platform VHDL/C++ simulation/verification environment PROVerify together with the employment of formal methods.
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© 2004 Springer-Verlag Berlin Heidelberg
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Heinkel, U., Mayer, C., Webb, C., Sahm, H., Haas, W., Gossens, S. (2004). An Optimized Flow for Designing High-Speed, Large-Scale CMOS ASIC SoCs. In: Pimentel, A.D., Vassiliadis, S. (eds) Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2004. Lecture Notes in Computer Science, vol 3133. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-27776-7_11
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DOI: https://doi.org/10.1007/978-3-540-27776-7_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22377-1
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