Abstract
In several digital signal processing algorithms, intermediate results between computational stages are reordered according to stride permutations. If such algorithms are computed in parallel with reduced number of processing elements where one element computes several computational nodes, the permutation, instead of being hardwired, requires a storage of intermediate data elements. In this paper, register-based permutation networks for stride permutations are proposed. The proposed networks are regular and scalable and they support any stride of power-of-two. In addition, the networks reach the minimum of register complexity, i.e., the number of registers, indicating area-efficiency.
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References
Bidet, E., Castelain, D., Joanblang, C., Senn, P.: A fast single-chip implementation of 8192 complex point FFT. IEEE Journal of Solid-State Circuits 30(3), 300–305 (1995)
Bóo, M., Argüello, F., Bruguera, J., Doallo, R., Zapata, E.: High-performance VLSI architecture for the Viterbi algorithm. IEEE Transactions on Communications 45(2), 168–176 (1997)
Shung, C.B., Lin, H.D., Cypher, R., Siegel, P.H., Thapar, H.K.: Area-efficient architectures for the Viterbi algorithm. Part I: Theory. IEEE Transactions on Communications 41(4), 636–644 (1993)
Parhi, K.K.: Systematic synthesis of DSP data format converters using life-time analysis and forward-backward register allocation. IEEE Transactions on Circuits and Systems – Part II: Analog and Digital Signal Processing 39(7), 423–440 (1992)
Majumdar, M., Parhi, K.K.: Design of data format converters using twodimensional register allocation. IEEE Transactions on Circuits and Systems – Part II: Analog and Digital Signal Processing 45(4), 504–508 (1998)
Bae, J., Prasanna, V.K.: Synthesis of area-efficient and high-throughput rate data format converters. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 6(4), 697–706 (1998)
Srivatsan, K., Chakrabarti, C., Lucke, L.: A new register allocation scheme for low-power data format converters. IEEE Transactions on Circuits and Systems – Part II: Analog and Digital Signal Processing 46(9), 1250–1253 (1999)
Granata, J., Conner, M., Tolimieri, R.: Recursive fast algorithms and the role of the tensor product. IEEE Transactions on Signal Processing 40(12), 2921–2930 (1992)
Carlach, J.C., Penard, P., Sicre, J.L.: TCAD: a 27 MHz 8 × 8 discrete cosine transform chip. In: Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing. Glasgow, UK, May 23–26, pp. 2429–2432 (1989)
Takala, J., Järvinen, T.: Multi-port interconnection networks for matrix transpose. In: Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Phoenix, AZ, U.S.A., May 26–29, pp. 874–877 (2002)
Takala, J., Järvinen, T., Salmela, P., Akopian, D.: Multi-port interconnection networks for radix-r algorithms. In: Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Salt Lake City, UT, U.S.A, May 7–11, pp. 1177–1180 (2001)
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Järvinen, T., Takala, J. (2004). Register-Based Permutation Networks for Stride Permutations. In: Pimentel, A.D., Vassiliadis, S. (eds) Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2004. Lecture Notes in Computer Science, vol 3133. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-27776-7_12
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DOI: https://doi.org/10.1007/978-3-540-27776-7_12
Publisher Name: Springer, Berlin, Heidelberg
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