Abstract
Reconfigurable computing architectures promise to substantially increase the performance of computations through the customization of data-path and storage structures best suited to the specific needs of each computation. The need to synthesize, either fully or partially, the structure of the target architecture while simultaneously attempting to optimize the mapping of the computation to that architecture creates a vast design space exploration (DSE) challenge. In this paper we describe current approaches to this DSE problem using program analysis, estimation, modeling and empirical optimization techniques. We also describe a unified approach for this DSE challenge in which these techniques can be complemented with history- and learning-based approaches.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Cronquist, D., et al.: Specifying and Compiling Applications for RaPiD. In. In: Proc. IEEE Symp. on FPGAs for Custom Computing Machines (FCCM 1998), pp.116–125 (1998)
XPP Technologies, Inc.: The XPP White Paper. Release 2.1.1 edn. (2002)
Hauser, J., Wawrzynek, J.: Garp: A MIPS Processor with a Reconfigurable Coprocessor. In: Proc. of the IEEE Symp. on FPGAs for Custom Computing Machines (1997)
Kulkarni, D., Najjar, W., Rinker, R., Kurdah, F.: Fast Area Estimation to Support Compiler Optimizations in FPGA-based Reconfigurable Systems. In: IEEE Symp. on Field-Programmable Custom Computing Machines, FCCM (2002)
Nayak, H.M., Choudhary, A., Banerjee, P.: Accurate Area and Delay Estimators for FPGAs. In: Proc. of the 2002 Design Automation and Test in Europe Conference and Exhibition (DATE 2002), IEEE Computer Society Press, Los Alamitos (2002)
Liao, J., Wong, W.F., Mitra, T.: A Model for the Hardware Realization of Loops. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 334–344. Springer, Heidelberg (2003)
Derrien, S., Rajoupadyhe, S.: Loop tiling for reconfigurable accelerators. In: Brebner, G., Woods, R. (eds.) FPL 2001. LNCS, vol. 2147, p. 398. Springer, Heidelberg (2001)
So, B., Hall, M., Diniz, P.: A Compiler Approach to Fast Hardware Design Space Exploration for FPGA Systems. In: Proc. of the 2002 ACM Conference on Programming Language Design and Implementation (PLDI 2002), ACM, New York (2002)
Kathail, V., Aditya, S., Schreiber, R., Rau, B., Cronquist, D., Sivaraman, M.: PICO: Automatically designing custom computers. IEEE Computer (2002)
Bakshi, A., Prasanna, V., Ledeczi, A.: MILAN: A Model Based Integrated Simulation Framework for Design of Embedded Systems. In: Proc. of the 2001 ACMWorkshop on Languages, Compilers, and Tools for Embedded Systems, LCTES 2001 (2001)
Halambi, A., et al.: EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability. In: Proc. of the Conf, on Design Automation and Test Europe, DATE 1999 (1999)
So, B., Hall, M.: Increasing the applicability of scalar replacement. In: Duesterwald, E. (ed.) CC 2004. LNCS, vol. 2985, pp. 185–201. Springer, Heidelberg (2004)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Diniz, P.C. (2004). Design Space Exploration for Configurable Architectures and the Role of Modeling, High-Level Program Analysis and Learning Techniques. In: Pimentel, A.D., Vassiliadis, S. (eds) Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2004. Lecture Notes in Computer Science, vol 3133. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-27776-7_23
Download citation
DOI: https://doi.org/10.1007/978-3-540-27776-7_23
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22377-1
Online ISBN: 978-3-540-27776-7
eBook Packages: Springer Book Archive