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Scalable FFT Processors and Pipelined Butterfly Units

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Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2004)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 3133))

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Abstract

This paper considers partial-column radix-2 FFT processors. The efficiency of processors based on bit-parallel multipliers, distributed arithmetic, and CORDIC is analyzed with the aid of logic synthesis.

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Author information

Authors and Affiliations

  1. Tampere University of Technology, P.O.Box 553, FIN-33101, Tampere, Finland

    Jarmo Takala & Konsta Punkka

Authors
  1. Jarmo Takala
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  2. Konsta Punkka
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Editor information

Editors and Affiliations

  1. Computer Systems Architecture Group, University of Amsterdam, The Netherlands

    Andy D. Pimentel

  2. Computer Engineering Lab, TUDelft., Postbus 5031, 2600 GA, Delft, The Netherlands

    Stamatis Vassiliadis

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© 2004 Springer-Verlag Berlin Heidelberg

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Takala, J., Punkka, K. (2004). Scalable FFT Processors and Pipelined Butterfly Units. In: Pimentel, A.D., Vassiliadis, S. (eds) Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2004. Lecture Notes in Computer Science, vol 3133. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-27776-7_39

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  • DOI: https://doi.org/10.1007/978-3-540-27776-7_39

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-22377-1

  • Online ISBN: 978-3-540-27776-7

  • eBook Packages: Springer Book Archive

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