Abstract
Future signal processing SoC designs will contain an increasing number of heterogeneous programmable units combined with a complex communication architecture to meet flexibility, performance and cost constraints. Designing such a heterogeneous MP-SoC architecture bears enormous potential for optimization, but requires a system-level design environment and methodology to evaluate architectural alternatives effectively.
Recently, efficient tool frameworks have been proposed to support the design space exploration for large scale embedded systems. The technique presented in this paper allows integrating retargeteable Instruction Set Simulators (ISS) into such an exploration framework very early in the design flow.
In a dual-processor JPEG decoding case study, we illustrate the effectiveness of this approach.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Grötker, T., Liao, S., Martin, G., Swan, S.: System Design with SystemC. Kluwer Academic Publishers, Dordrecht (2002)
Ariyamparambath, M., Bussagila, D., Reinkemeier, B., et al.: A Highly Efficient Modeling Style for Heterogeneous Bus Architectures. In: International Symposium on System-on- Chip, Tampere (Finland) (November 2003)
Zivkovic, V.D., Deprettere, E., de Kock, E., van de Wolf, P.: Fast and Accurate Multiprocessor Architecture Exploration with Symbolic Programs. In: Proc. Int. Conf. on Design, Automation and Test in Europe(DATE) (2003)
Gajski, D., Zhu, J., Dömer, R., Gerstlauer, A., Zhao, S.: SpecC: Specification Language and Methodology. Kluwer Academic Publishers, Dordrecht (2000)
Kogel, T., Doerper, M., Wieferink, A., et al.: A Modular Simulation Framework for Architectural Exploration of On-Chip Interconnection Networks. In: The First IEEE/ACM/IFIP International Conference on HW/SW Codesign and System Synthesis, Newport Beach ,California, USA (October 2003)
Notbauer, J., Albrecht, T., Niedrist, G., Rohringer, S.: Verification and management of a multimillion-gate embedded core design. In: DAC (1999)
Paulin, P., Magarshack, P.: System-on-chip beyond the nanometer wall. In: DAC (2003)
Cesario, W., Baghdadi, A., Gauthier, L., et al.: Component-Based Design Approach for Multicore SoCs. In: DAC (2002)
Wieferink, A., Kogel, T., Braun, G., et al.: A System Level Processor/Communication Co- Exploration Methodology for Multi-Processor System-on-Chip Platforms. In: Proceedings of the Conference on Design, Automation & Test in Europe (DATE), Paris, France (February 2004)
Hoffmann, A., Kogel, T., Nohl, A., et al.: A Novel Methodology for the Design of Application Specific Instruction-Set Processor Using a Machine Description Language. IEEE Transactions on Computer-Aided Design of Integrated Cicuits and Systems (TCAD) 20(11), 1338–1354 (2001)
Hadjiyiannis, G., Devadas, S.: Techniques for Accurate Performance Evaluation in Architecture Exploration. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (2003)
Mishra, P., Grun, P., Dutt, N., Nicolau, A.: Processor-memory co-exploration driven by an architectural description language. In: Intl. Conf. on VLSI Design (2001)
Fauth, A., Van Praet, J., Freericks, M.: Describing Instruction Set Processors Using nML. In: Proceedings of the European Design & Test Conference (March 1995)
Leupers, R.: HDL-based Modeling of Embedded Processor Behavior for Retargetable Compilation. In: Proc. Int. Symp. on System Synthesis (September 1998)
Hohenauer, M., Scharwaechter, H., Karuri, K., et al.: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. In: Proceedings of the Conference on Design, Automation & Test in Europe (DATE), Paris, France (February 2004)
SystemC initiative, http://www.systemc.org
Kogel, T., Wieferink, A., Leupers, R., et al.: Virtual Architecture Mapping: A SystemC based Methodology for Architectural Exploration of System-on-Chip Designs. In: Int.Workshop on Systems, Architecturs, Modeling and Simulation (SAMOS), Samos ,Greece (July 2003)
LISATek Product Line. CoWare, http://www.coware.com
Wieferink, A., Kogel, T., Nohl, A., et al.: A Generic Toolset for SoC Multiprocessor Debugging and Synchronisation. In: IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), The Hague ,Netherlands (June 2003)
Official JPEG homepage, http://www.jpeg.org
ConvergenSC. CoWare, http://www.coware.com
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Wieferink, A., Doerper, M., Kogel, T., Leupers, R., Ascheid, G., Meyr, H. (2004). Early ISS Integration into Network-on-Chip Designs. In: Pimentel, A.D., Vassiliadis, S. (eds) Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2004. Lecture Notes in Computer Science, vol 3133. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-27776-7_46
Download citation
DOI: https://doi.org/10.1007/978-3-540-27776-7_46
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-22377-1
Online ISBN: 978-3-540-27776-7
eBook Packages: Springer Book Archive