Abstract
In this paper, the architecture of a high-performance 32-bit fixed-point DSP called DSP3000 is proposed and implemented. The DSP3000 employs super-Harvard architecture and can issue three memory access operations in a single clock cycle. The processor has eight pipe stages with separated memory read and write stages, which alleviate the data dependency problems and improve the execution efficiency. The processor also possesses a modulo addressing unit with optimized structure to enhance the address generation speed. A fully pipelined MAC (Multiply Accumulate) unit is incorporated in the design, which enables 32×32+72 MAC operation in a single clock cycle. The processor is implemented with SMIC 0.18μm 1.8V 1P6M process and has a core size of 2.2mm by 2.4mm. Test result shows that it can operate at a maximum frequency of 300MHz with the average power consumption of 30mw/100MHz.
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© 2004 Springer-Verlag Berlin Heidelberg
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Chen, J., Xu, R., Fu, Y. (2004). Architecture Design of a High-Performance 32-Bit Fixed-Point DSP. In: Yew, PC., Xue, J. (eds) Advances in Computer Systems Architecture. ACSAC 2004. Lecture Notes in Computer Science, vol 3189. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30102-8_10
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DOI: https://doi.org/10.1007/978-3-540-30102-8_10
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23003-8
Online ISBN: 978-3-540-30102-8
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