Abstract
In this paper we present an victim cache design for caches organized with line that contains multiple sectors (sector cache). Sector caches use less memory bits to store tags than non-sectored caches. Victim cache has been proposed to alleviate conflict misses in a lower associative cache design. This paper examines how victim cache can be implemented in a sector cache and proposes a further optimization of the victim buffer design in which only the tags of the victim lines are remembered to re-use data in the sector cache. This design is more efficient because only an additional “OR” operation is needed in the tag checking critical path. We use a full system simulator to generate traces and a cache simulator to compare the miss ratios of different victim cache designs in sector caches. Simulation results show that this proposed design has comparable miss ratios with designs having much more complexity.
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References
Seznec, A.: Decoupled sectored caches. IEEE Trans. on Computers (February 1997)
Patterson, D.A., Hennessy, J.L.: Computer architecture: A quantitative approach. Morgan Kaufmann Publishers Inc., San Francisco (1996)
Liu, K.-C., King, C.-T.: On the effectiveness of sectored caches in reducing false sharing misses. In: International Conference on Parallel and Distributed Systems (1997)
Hong, W.-K., Han, T.-D., Kim, S.-D., Yang, S.-B.: An Effective Full-Map Directory Scheme for the Sectored Caches, In: International Conference/ Exhibition on High Performance Computing in Asia Pacific Region (1997)
Hinton, G., Sager, D., Upton, M., Boggs, D., Carmean, D., Kyker, A., Roussel, P.: The Microarchitecture of the Pentium® 4 processor. In: Intel Technology Journal (1st quarter 2001), http://developer.intel.com/technology/itj/q12001/articles/art_2.htm
UltraSPARCTM Iii User’s Manual, Sun Microsystems (1999)
PowerPCTM, MPC7400 RISC Microprocessor Technical Summary, Mororola, Order Number: MPC7400TS/D, Rev. 0, 8/1999
Kartunov, V.: IBM PowerPC G5: Another World, X-bit Labs (January 2004), http://www.xbitlabs.com/articles/cpu/display/powerpc-g5_6.html
Jouppi, N.: Improving direct-mapped cache performance by the addition of a small fully associative cache and prefetch buffers. In: International Symposium on Computer Architecture (1990)
Rothman, J.B., Smith, A.J.: Sector Cache Design and Performance. In: International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (2000)
Seznec, A.: Decoupled sectored caches: conciliating low tag implementation cost. In: International Symposium on. Computer Architecture (1994)
Lipty, J.S.: Structural Aspects of the System/360 Model 85, Part II: The Cache. IBM Systems Journal 7 (1968)
Rothman, J.B., Smith, A.J.: The Pool of SubSectors Cache Design. In: International Conference on Supercomputing (1999)
Hill, M.D., Smith, A.J.: Experimental Evaluation of On-Chip Microprocessor Cache Memories. In: International Symposium on Computer Architecture (June 1984)
Goodman, J.R.: Using Cache Memory to Reduce Processor Memory Traffic. In: International Symposium on Computer Architecture (1983)
Albera, G., Bahar, R.: Power/performance Advantages of Victim Buffer in High- Performance Processors. In: IEEE Alessandro Volta Memorial Workshop on Low-Power Design (1999)
Shafai, F., Schultz, K.J., Randall Gibson, G.F., Bluschke, A.G., Somppi, D.E.: Fully Parallel 30-MHz, 2.5-Mb CAM. IEEE journal of solid-state circuits 33(11) (November 1998)
SPEC CPU 2000 (2000), http://www.specbench.org/osg/cpu2000
SPEC JBB 2000 (2000), http://www.specbench.org/jbb2000
Lai, C., Lu, S., Zhao, Q.: Performance Analysis of Speech Recognition Software. In: Workshop on Computer Architecture Evaluation using Commercial Workloads, International Symposium on High Performance Computer Architecture (2002)
Song, J., Li, J., Chen, Y.-K.: Quality-Delay and Computation Trade-Off Analysis of Acoustic Echo Cancellation On General-Purpose CPU. In: International Conference on Acoustics, Speech, and Signal Processing (2003)
Uhlig, R., et al.: SoftSDV: A Pre-silicon Software Development Environment for the IA 64 Architecture. Intel Technology Journal (4th quarter 1999), http://developer.intel.com/technology/itj/q41999/articles/art_2.htm
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Lai, C., Lu, SL. (2004). Efficient Victim Mechanism on Sector Cache Organization. In: Yew, PC., Xue, J. (eds) Advances in Computer Systems Architecture. ACSAC 2004. Lecture Notes in Computer Science, vol 3189. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30102-8_3
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DOI: https://doi.org/10.1007/978-3-540-30102-8_3
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23003-8
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